Generating a timeout signal based on a clock counter associated with a data request
    1.
    发明授权
    Generating a timeout signal based on a clock counter associated with a data request 有权
    基于与数据请求相关联的时钟计数器生成超时信号

    公开(公告)号:US09372500B2

    公开(公告)日:2016-06-21

    申请号:US14191923

    申请日:2014-02-27

    CPC classification number: G06F1/04 G06F11/0745 G06F11/0757 G06F13/4027

    Abstract: Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.

    Abstract translation: 各种方面提供了基于与数据请求相关联的时钟计数器生成超时信号。 接口组件被配置为从主设备接收数据请求并将数据请求转发到从设备。 超时组件被配置用于在接收到与来自从设备的数据请求相关联的数据响应之前响应于确定与时钟计数器相关联的阈值电平来保持与数据请求相关联的时钟计数器并产生超时信号 。

    GENERATING A TIMEOUT SIGNAL BASED ON A CLOCK COUNTER ASSOCIATED WITH A DATA REQUEST
    2.
    发明申请
    GENERATING A TIMEOUT SIGNAL BASED ON A CLOCK COUNTER ASSOCIATED WITH A DATA REQUEST 有权
    根据与数据请求相关的时钟计数器产生超时信号

    公开(公告)号:US20150323956A1

    公开(公告)日:2015-11-12

    申请号:US14191923

    申请日:2014-02-27

    CPC classification number: G06F1/04 G06F11/0745 G06F11/0757 G06F13/4027

    Abstract: Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.

    Abstract translation: 各种方面提供了基于与数据请求相关联的时钟计数器生成超时信号。 接口组件被配置为从主设备接收数据请求并将数据请求转发到从设备。 超时组件被配置用于在接收到与来自从设备的数据请求相关联的数据响应之前响应于确定与时钟计数器相关联的阈值电平来保持与数据请求相关联的时钟计数器并产生超时信号 。

    END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS
    3.
    发明申请
    END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS 审中-公开
    芯片互连系统端到端流控制

    公开(公告)号:US20150032794A1

    公开(公告)日:2015-01-29

    申请号:US13953059

    申请日:2013-07-29

    CPC classification number: H04L47/215 H04L47/2408

    Abstract: Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first.

    Abstract translation: 提供了一种用于片上系统接口的端到端流控制管理。 由于令牌被注入到安排在计算机网络中的代理中,令牌的输入点被动态地改变,使得令牌并不总是被注入同一个代理。 附加地或替代地,当令牌被注入到令牌环中时,令牌最初不被激活,直到发生预定事件(例如,在特定数量的跳数之后)。 附加地或替代地,还提供了一个空闲池管理器,其可以首先通过消耗较低优先级时隙来保持至少一些高优先级时隙可用。

Patent Agency Ranking