公开(公告)号：US20160164526A1

公开(公告)日：2016-06-09

申请号：US14903428

申请日：2014-07-08

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Sarma Vrudhula ,  Niranjan Kulkarni

IPC: H03K19/177 ,  H03K19/23 ,  H03K19/00

CPC classification number: H03K19/1778 ,  H03K19/0013 ,  H03K19/17736 ,  H03K19/17768 ,  H03K19/23

Abstract: A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.

Abstract translation: 现场可编程阈值逻辑阵列（FPTLA）包括多个阈值逻辑门和多个可编程互连元件。 每个可编程互连元件连接在两个或更多个阈值逻辑门之间，使得可编程互连元件在阈值逻辑门之间路由信号。 通过使用FPTLA的阈值逻辑门，FPTLA的大小可能会明显小于传统的解决方案。 此外，与常规解决方案相比，使用阈值逻辑门导致FPTLA的计算速度显着提高。

公开(公告)号：US09490815B2

公开(公告)日：2016-11-08

申请号：US14903428

申请日：2014-07-08

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Sarma Vrudhula ,  Niranjan Kulkarni

IPC: H03K19/23 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/1778 ,  H03K19/0013 ,  H03K19/17736 ,  H03K19/17768 ,  H03K19/23

Abstract: A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.

Abstract translation: 现场可编程阈值逻辑阵列（FPTLA）包括多个阈值逻辑门和多个可编程互连元件。 每个可编程互连元件连接在两个或更多个阈值逻辑门之间，使得可编程互连元件在阈值逻辑门之间路由信号。 通过使用FPTLA的阈值逻辑门，FPTLA的大小可能会明显小于传统的解决方案。 此外，与常规解决方案相比，使用阈值逻辑门导致FPTLA的计算速度显着提高。