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    CONFIGURABLE BNN ASIC USING A NETWORK OF PROGRAMMABLE THRESHOLD LOGIC STANDARD CELLS
    1.
    发明申请
    CONFIGURABLE BNN ASIC USING A NETWORK OF PROGRAMMABLE THRESHOLD LOGIC STANDARD CELLS 有权

    公开(公告)号：US20220121915A1

    公开(公告)日：2022-04-21

    申请号：US17504279

    申请日：2021-10-18

    Applicant: Arizona Board of Regents on behalf of Arizona State University ,  The Texas A&M University System

    Inventor： Ankit Wagle ,  Sarma Vrudhula ,  Sunil Khatri

    IPC: G06N3/063 ,  G06N3/04

    Abstract: A configurable binary neural network (BNN) application-specific integrated circuit (ASIC) using a network of programmable threshold logic standard cells is provided. A new architecture is presented for a BNN that uses an optimal schedule for executing the operations of an arbitrary BNN. This architecture, also referred to herein as TULIP, is designed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a single instruction, multiple data (SIMD) fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. Novel algorithms are presented herein for mapping arbitrary nodes of a BNN onto the TULIP-PEs. Comparison results show that TULIP is consistently 3× more energy-efficient than conventional designs, without any penalty in performance, area, or accuracy.

    ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY
    2.
    发明申请
    ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY 有权
    坚固，低功耗，可重新启动的阈值逻辑阵列

    公开(公告)号：US20160164526A1

    公开(公告)日：2016-06-09

    申请号：US14903428

    申请日：2014-07-08

    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

    Inventor： Sarma Vrudhula ,  Niranjan Kulkarni

    IPC: H03K19/177 ,  H03K19/23 ,  H03K19/00

    CPC classification number: H03K19/1778 ,  H03K19/0013 ,  H03K19/17736 ,  H03K19/17768 ,  H03K19/23

    Abstract: A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.

    Abstract translation: 现场可编程阈值逻辑阵列（FPTLA）包括多个阈值逻辑门和多个可编程互连元件。 每个可编程互连元件连接在两个或更多个阈值逻辑门之间，使得可编程互连元件在阈值逻辑门之间路由信号。 通过使用FPTLA的阈值逻辑门，FPTLA的大小可能会明显小于传统的解决方案。 此外，与常规解决方案相比，使用阈值逻辑门导致FPTLA的计算速度显着提高。

    Robust, low power, reconfigurable threshold logic array
    4.
    发明授权
    Robust, low power, reconfigurable threshold logic array 有权
    稳健，低功耗，可重新配置的阈值逻辑阵列

    公开(公告)号：US09490815B2

    公开(公告)日：2016-11-08

    申请号：US14903428

    申请日：2014-07-08

    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

    Inventor： Sarma Vrudhula ,  Niranjan Kulkarni

    IPC: H03K19/23 ,  H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/1778 ,  H03K19/0013 ,  H03K19/17736 ,  H03K19/17768 ,  H03K19/23

    Abstract: A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.

    Abstract translation: 现场可编程阈值逻辑阵列（FPTLA）包括多个阈值逻辑门和多个可编程互连元件。 每个可编程互连元件连接在两个或更多个阈值逻辑门之间，使得可编程互连元件在阈值逻辑门之间路由信号。 通过使用FPTLA的阈值逻辑门，FPTLA的大小可能会明显小于传统的解决方案。 此外，与常规解决方案相比，使用阈值逻辑门导致FPTLA的计算速度显着提高。

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