公开(公告)号：US09171634B2

公开(公告)日：2015-10-27

申请号：US13827815

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Bo Zheng ,  Gus Yeung ,  Fakhruddin ali Bohra

IPC: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。

公开(公告)号：US20140269091A1

公开(公告)日：2014-09-18

申请号：US13827815

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Bo ZHENG ,  Gus Yeung ,  Fakhruddin ali Bohra

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。