公开(公告)号：US20140269091A1

公开(公告)日：2014-09-18

申请号：US13827815

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Bo ZHENG ,  Gus Yeung ,  Fakhruddin ali Bohra

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。

公开(公告)号：US20150085586A1

公开(公告)日：2015-03-26

申请号：US14037413

申请日：2013-09-26

Applicant: ARM LIMITED

Inventor： Bo ZHENG ,  Jungtae KWON ,  Gus YEUNG ,  Yew Keong CHONG

IPC: G11C7/12 ,  G06F17/50

CPC classification number: G11C7/12 ,  G11C7/1096

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号识别哪个列包含寻址的存储器单元。

公开(公告)号：US20140250278A1

公开(公告)日：2014-09-04

申请号：US13782077

申请日：2013-03-01

Applicant: ARM LIMITED

Inventor： Gus YEUNG ,  Bo ZHENG ,  Frank GUO

IPC: G11C7/00 ,  G06F12/00

CPC classification number: G06F12/00 ,  G11C5/147 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/417

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Abstract translation: 集成电平移位锁存电路接收第一电压域中的输入信号并在第二电压域中产生输出信号。 数据保持电路在透明阶段工作，其中数据值经受电平移位功能，并根据输入信号写入数据保持电路。 控制电路控制数据保持电路在时钟信号的第一阶段期间在透明阶段中工作，并且在时钟信号的第二阶段期间操作在锁存阶段。 写入电路将数据值写入数据保持电路。 竞争缓解电路在透明阶段期间减少数据保持电路内的至少一个组件的压降。