公开(公告)号：US20220066840A1

公开(公告)日：2022-03-03

申请号：US17446796

申请日：2021-09-02

Applicant: Arm Limited

Inventor： Mark Salling RUTLAND ,  Gareth Rhys STOCKWELL ,  Christoffer DALL ,  Jade Ella Carla ALGLAVE

IPC: G06F9/52 ,  G06F9/48

Abstract: Apparatus comprises a data memory to store lock data for each of a set of processing resources, the lock data representing lock status data and tag data indicating a resource type selected from a plurality of resource types; and a processing element to execute an atomic operation with respect to the lock data for a given processing resource, the atomic operation comprising at least: a detection of whether the given processing resource is of a required resource type; a detection from the lock status data whether the given processing resource is currently unlocked; and when the given processing resource is detected to be currently unlocked and of the required resource type, performance of a predetermined action with respect to one or both of the lock status data and the tag data.

公开(公告)号：US20200226061A1

公开(公告)日：2020-07-16

申请号：US16647659

申请日：2018-10-11

Applicant: ARM Limited

Inventor： Jason PARKER ,  Djordje KOVACEVIC ,  Gareth Rhys STOCKWELL ,  Matthew Lucien EVANS

IPC: G06F12/02 ,  G06F12/14

Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.

公开(公告)号：US20200159677A1

公开(公告)日：2020-05-21

申请号：US16625924

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien EVANS ,  Jason PARKER ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/0891 ,  G06F12/0802

Abstract: An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.

公开(公告)号：US20200150970A1

公开(公告)日：2020-05-14

申请号：US16625912

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien EVANS ,  Jason PARKER ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07

Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). In response to a first variant of an exception return instruction the processing circuitry (8) returns from processing of an exception while staying within the same realm. In response to a second variant of the exception return instruction the processing circuitry switches processing from a current realm to a destination realm.

公开(公告)号：US20200371966A1

公开(公告)日：2020-11-26

申请号：US16623528

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Matthew Lucien EVANS ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F9/455

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.

公开(公告)号：US20200278801A1

公开(公告)日：2020-09-03

申请号：US16648901

申请日：2018-11-09

Applicant: ARM Limited

Inventor： Jason PARKER ,  Martin WEIDMANN ,  Gareth Rhys STOCKWELL ,  Matthew Lucien EVANS

IPC: G06F3/06 ,  G06F21/62

Abstract: A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation table 908 stored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.

公开(公告)号：US20200174950A1

公开(公告)日：2020-06-04

申请号：US16625943

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Matthew Lucien EVANS ,  Gareth Rhys STOCKWELL ,  Djordje KOVACEVIC

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/62

Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). A realm management unit (RMU) (20) is provided to perform realm management operations for managing the realms. The memory access circuitry (26) controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU (20).