公开(公告)号：US20250036575A1

公开(公告)日：2025-01-30

申请号：US18914382

申请日：2024-10-14

Applicant: Arm Limited

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/109

Abstract: Processing circuitry 10 performs processing in one of at least three domains 82, 84, 86, 88. Address translation circuitry 16 translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces 61 selected based at least on the current domain. The domains include a root domain 82 for managing switching between other domains. The physical address spaces 61 include a root physical address space associated with the root domain 82, separate from physical address spaces associated with other domains.

公开(公告)号：US20230176983A1

公开(公告)日：2023-06-08

申请号：US17906625

申请日：2021-01-26

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1045 ,  G06F12/0808

CPC classification number: G06F12/1425 ,  G06F12/1458 ,  G06F12/1063 ,  G06F12/0808

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

公开(公告)号：US20200218673A1

公开(公告)日：2020-07-09

申请号：US16647642

申请日：2018-12-10

Applicant: ARM Limited

Inventor： Jason PARKER ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F21/62 ,  G06F12/1009 ,  G06F12/1027

Abstract: A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.

公开(公告)号：US20200371966A1

公开(公告)日：2020-11-26

申请号：US16623528

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Matthew Lucien EVANS ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F9/455

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.

公开(公告)号：US20200278801A1

公开(公告)日：2020-09-03

申请号：US16648901

申请日：2018-11-09

Applicant: ARM Limited

Inventor： Jason PARKER ,  Martin WEIDMANN ,  Gareth Rhys STOCKWELL ,  Matthew Lucien EVANS

IPC: G06F3/06 ,  G06F21/62

Abstract: A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation table 908 stored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.

公开(公告)号：US20210271512A1

公开(公告)日：2021-09-02

申请号：US17056896

申请日：2019-05-01

Applicant: Arm Limited

Inventor： Timothy Nicholas HAY ,  Martin WEIDMANN ,  Michael Alexander KENNEDY ,  Andrew John TURNER

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F9/455

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

公开(公告)号：US20200159677A1

公开(公告)日：2020-05-21

申请号：US16625924

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien EVANS ,  Jason PARKER ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/0891 ,  G06F12/0802

Abstract: An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.

公开(公告)号：US20200150970A1

公开(公告)日：2020-05-14

申请号：US16625912

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien EVANS ,  Jason PARKER ,  Gareth Rhys STOCKWELL ,  Martin WEIDMANN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07

Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). In response to a first variant of an exception return instruction the processing circuitry (8) returns from processing of an exception while staying within the same realm. In response to a second variant of the exception return instruction the processing circuitry switches processing from a current realm to a destination realm.