公开(公告)号：US20190088307A1

公开(公告)日：2019-03-21

申请号：US15711116

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Nigel John STEPHENS ,  Lee Evan EISEN ,  Jaime FERRAGUT MARTINEZ-VARA DE REY

IPC: G11C11/4094 ,  G11C11/56

CPC classification number: G11C11/4094 ,  G06F9/30 ,  G11C7/1006 ,  G11C11/5621 ,  G11C19/28 ,  G11C19/38

Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.