公开(公告)号：US20150371959A1

公开(公告)日：2015-12-24

申请号：US14307574

申请日：2014-06-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK

IPC: H01L23/58 ,  G06F17/50

CPC classification number: H01L23/58 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

Abstract translation: 集成电路2形成有由电网导体20覆盖的标准单元电力导体14.电网导体相对于其下面的标准单元电力导体在横向于电力电网导体的纵向轴线的方向上偏移 。 这具有增加对电网导体的一侧可能的导体间隔的作用。 因此，可以提供宽度比最小宽度的电网导体，其仅阻挡其相邻轨道位置中的一个被路由导体22使用。

公开(公告)号：US20170185709A1

公开(公告)日：2017-06-29

申请号：US15456634

申请日：2017-03-13

Applicant: ARM Limited

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US20160357894A1

公开(公告)日：2016-12-08

申请号：US15239991

申请日：2016-08-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.