公开(公告)号：US20170185709A1

公开(公告)日：2017-06-29

申请号：US15456634

申请日：2017-03-13

Applicant: ARM Limited

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US20150370955A1

公开(公告)日：2015-12-24

申请号：US14307646

申请日：2014-06-18

Applicant: ARM LIMITED

Inventor： Lena AHLEN

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Abstract translation: 一种静态时序分析方法，用于确定集成电路设计中目标单元周围的预期设计条件。 基于目标小区的预期设计条件和表示默认设计条件的传播延迟变化​​的定时降额来确定降额调整，然后基于降额调整来调整。 基于经调整的定时降额来确定包括目标小区的信号路径的期望定时。 可以基于针对预期设计条件的通过目标小区的传播延迟的模拟方差来确定降额调整。 这种方法避免了定时降额的不必要的乐观或悲观，这减少了静态时序分析中定时违规的假阳性或假阴性检测的数量。

公开(公告)号：US20160357894A1

公开(公告)日：2016-12-08

申请号：US15239991

申请日：2016-08-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne FREDERICK, JR. ,  Karen Lee DELK ,  Lena AHLEN ,  James Dennis DODRILL

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.