公开(公告)号：US09361112B2

公开(公告)日：2016-06-07

申请号：US13865371

申请日：2013-04-18

Applicant: ARM Limited

Inventor： Clément Marc Demongeot ,  Louis-Marie Vincent Mouton ,  Frédéric Claude Marie Piry ,  Jocelyn Francois Orion Jaubert ,  Albin Pierick Tonnerre

IPC: G06F9/30 ,  G06F7/38 ,  G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3806

Abstract: A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed.

Abstract translation: 数据处理装置执行呼叫指令，并且在响应于呼叫指令执行的指令序列之后，返回指令使程序流程返回到与该呼叫指令相关联的程序序列中的一个点。 数据处理装置被配置为根据早期指令的预测结果推测执行指令，并且返回地址预测单元被配置为存储与未解决的呼叫指令相关联的返回地址。 返回地址预测单元包括：堆栈部分，在其上推送与未解决的呼叫指令相关联的返回地址，并且当推测性地执行返回指令时从该地址弹出返回地址; 以及缓冲部分，其存储针对执行的每个未解决的调用指令的条目和针对被推测执行的每个返回指令。

公开(公告)号：US09323536B2

公开(公告)日：2016-04-26

申请号：US13875704

申请日：2013-05-02

Applicant: ARM LIMITED

Inventor： Clement Marc Demongeot ,  Louis-Marie Vincent Mouton ,  Jocelyn Francois Orion Jaubert

IPC: G06F9/00 ,  G06F9/44 ,  G06F9/34 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/3806

Abstract: A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack.

Abstract translation: 公开了一种数据处理装置和数据处理方法。 提取单元检索包括来自存储器的调用指令和返回指令以由执行单元执行的程序指令。 分支预测单元参考返回地址堆栈生成针对所标识的返回指令的返回地址预测。 当执行单元执行呼叫指令并且当执行单元执行返回指令时，从返回地址堆栈执行返回地址弹出时，分支预测单元执行到所述返回地址堆栈的返回地址推送。 错误检测单元通过参考返回地址预测来识别所述程序指令中的缺失的调用指令或缺少的返回指令，当执行返回指令时由执行单元指示的解析返回地址和返回地址堆栈的内容。

公开(公告)号：US09311088B2

公开(公告)日：2016-04-12

申请号：US13927552

申请日：2013-06-26

Applicant: ARM Limited

Inventor： Frederic Claude Marie Piry ,  Louis-Marie Vincent Mouton ,  Luca Scalabrino ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/30098 ,  G06F9/3012 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/45558

Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.

Abstract translation: 提供了一种用于执行寄存器重命名的装置和方法。 提供可用的寄存器识别电路以识别哪些物理寄存器形成可由寄存器重命名电路映射到由要执行的指令指定的架构寄存器的物理寄存器池。 存储其值在处理电路的操作期间被修改的配置数据，使得当配置数据具有第一值时，配置数据识别架构寄存器集合的至少一个体系结构寄存器，其不需要映射到物理寄存器 寄存器重命名电路。 寄存器识别电路被布置为引用修改的数据值，使得当配置数据具有第一值时，由于需要映射到物理寄存器的架构寄存器的数量的减少，池中的物理寄存器的数量增加 。