公开(公告)号：US20150317763A1

公开(公告)日：2015-11-05

申请号：US14700026

申请日：2015-04-29

Applicant: ARM Limited

Inventor： Alexis Mather ,  Sean Ellis

IPC: G06T1/20

CPC classification number: G06T15/005 ,  G06T1/60

Abstract: A tile based graphics processing pipeline comprises a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a processing stage 6 operable to receive rendered fragment data 3, and to perform a processing operation using the rendered fragment data to generate per-tile metadata 7.

Abstract translation: 基于瓦片的图形处理流水线包括多个处理阶段，包括至少光栅化器，其光栅化输入基元以生成要处理的图形片段;以及渲染器，其处理由光栅器生成的片段以产生渲染片段数据，以及处理阶段 6，用于接收渲染的片段数据3，并且使用所渲染的片段数据来执行处理操作以生成每片元数据7。

公开(公告)号：US20140368521A1

公开(公告)日：2014-12-18

申请号：US14267969

申请日：2014-05-02

Applicant: ARM Limited

Inventor： Anders Lassen ,  Jorn Nystad ,  Alexis Mather ,  Sean Tristram Ellis

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G09G5/39 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

公开(公告)号：US10235792B2

公开(公告)日：2019-03-19

申请号：US14700026

申请日：2015-04-29

Applicant: ARM Limited

Inventor： Alexis Mather ,  Sean Ellis

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

Abstract: A tile based graphics processing pipeline comprises a plurality of processing stages, including at least a rasterizer that rasterizes input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasterizer to generate rendered fragment data, and a processing stage 6 operable to receive rendered fragment data 3, and to perform a processing operation using the rendered fragment data to generate per-tile metadata 7.

公开(公告)号：US09741089B2

公开(公告)日：2017-08-22

申请号：US14267969

申请日：2014-05-02

Applicant: ARM Limited

Inventor： Anders Lassen ,  Jorn Nystad ,  Alexis Mather ,  Sean Tristram Ellis

IPC: G09G5/39 ,  G06T15/00 ,  G06T11/00 ,  G06T1/60 ,  G06T1/20 ,  G06T11/40

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G09G5/39 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.