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公开(公告)号：US20150317763A1
公开(公告)日：2015-11-05
申请号：US14700026
申请日：2015-04-29
Applicant: ARM Limited
Inventor： Alexis Mather , Sean Ellis
IPC: G06T1/20
CPC classification number: G06T15/005 , G06T1/60
Abstract: A tile based graphics processing pipeline comprises a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a processing stage 6 operable to receive rendered fragment data 3, and to perform a processing operation using the rendered fragment data to generate per-tile metadata 7.
Abstract translation: 基于瓦片的图形处理流水线包括多个处理阶段，包括至少光栅化器，其光栅化输入基元以生成要处理的图形片段;以及渲染器，其处理由光栅器生成的片段以产生渲染片段数据，以及处理阶段 6，用于接收渲染的片段数据3，并且使用所渲染的片段数据来执行处理操作以生成每片元数据7。
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公开(公告)号：US10235792B2
公开(公告)日：2019-03-19
申请号：US14700026
申请日：2015-04-29
Applicant: ARM Limited
Inventor： Alexis Mather , Sean Ellis
Abstract: A tile based graphics processing pipeline comprises a plurality of processing stages, including at least a rasterizer that rasterizes input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasterizer to generate rendered fragment data, and a processing stage 6 operable to receive rendered fragment data 3, and to perform a processing operation using the rendered fragment data to generate per-tile metadata 7.
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公开(公告)号：US20150339852A1
公开(公告)日：2015-11-26
申请号：US14717850
申请日：2015-05-20
Applicant: ARM Limited
Inventor： Edward Plowman , Sean Ellis
CPC classification number: G06T17/20 , G06T15/005 , G06T15/80 , G06T2210/36 , G06T2215/12
Abstract: When rendering a region of a three-dimensional object represented by a base set of polygon vertices in a graphics processing pipeline, a first processing stage uses meta-information representative of the surface relief of the region of the three-dimensional object to determine whether to generate a set of additional polygon vertices over the region of the three-dimensional object, and generates the additional set of polygon vertices (when this is deemed necessary). A second processing stage then uses information representative of the surface relief of the region of the three-dimensional object to modify the positions of one or more of the polygon vertices, before the vertices are assembled into primitives that are then rasterised and rendered.
Abstract translation: 当在图形处理流水线中渲染由多边形顶点的基本集合表示的三维对象的区域时，第一处理阶段使用表示三维对象的区域的表面浮雕的元信息来确定是否 在三维对象的区域上生成一组附加的多边形顶点，并生成附加的多边形顶点集合（当需要时）。 然后，在将顶点组装成然后被光栅化和渲染的图元之前，第二处理阶段使用表示三维对象的区域的表面浮雕的信息来修改一个或多个多边形顶点的位置。
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公开(公告)号：US10194156B2
公开(公告)日：2019-01-29
申请号：US14793907
申请日：2015-07-08
Applicant: ARM LIMITED
Inventor： Daren Croxford , Sean Ellis , Ben James
IPC: H04N19/503 , H04N19/14 , H04N19/172 , G06T1/00 , H04N19/176 , H04N19/137 , H04N19/85 , H04N19/184
Abstract: A method and an apparatus are provided for generating an output frame from an input frame, in which the input frame is processed when generating the output frame. A region of a current input frame is compared with a region of a preceding input frame to determine if the region of the current input frame is similar to the region of the preceding input frame. When the region of the current input frame is determined to be similar to the region of the preceding input frame, information relating to processing performed on the region of the preceding input frame when generating a region of a preceding output frame is read, wherein the information is generated during the processing on the region of the preceding input frame. When the information indicates that the processing is unnecessary, a part or all of the processing of the region of the current input frame can be bypassed or eliminated.
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Patent Agency Ranking
公开(公告)号：US20130076761A1
公开(公告)日：2013-03-28
申请号：US13623744
申请日：2012-09-20
Applicant: ARM Limited
Inventor： Sean Ellis , Andreas Engh-halstvedt , Jorn Nystad
IPC: G06F15/16
CPC classification number: G06F15/16 , G06F9/5083 , G06T1/20 , G06T11/40
Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.
Abstract translation: 在具有多个渲染处理器的基于瓦片的图形处理系统中，要处理以生成用于显示的输出帧30的瓦片组31在不同的渲染处理器之间通过定义相应的瓦片穿越路径32,33,34,35进行划分，用于 每个渲染处理器从最初分配给处理器的瓦片开始，并且至少对于沿着路径的初始瓦片，遍历输出中的空间相邻的瓦片，并且如果跟随到它们的结尾，则遍历要渲染的每个瓦片。 然后，将待处理的给定渲染处理器的下一个图块选择为沿其定义的路径的下一个图块，除非路径中的下一个图块已经被另一个渲染处理器处理（或已被处理），在这种情况下 将要分配给渲染处理器的下一个瓦片选择为该处理器的瓦片穿越路径中的另外的空闲瓦片。
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公开(公告)号：US10825128B2
公开(公告)日：2020-11-03
申请号：US14822605
申请日：2015-08-10
Applicant: ARM Limited
Inventor： Daren Croxford , Ben James , Sean Ellis , Edward Charles Plowman
Abstract: A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer 15 by writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitry 14 arranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitry 16 arranged to acquire meta-data from the compressed block of data, and processing circuitry 21 arranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.
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公开(公告)号：US10089782B2
公开(公告)日：2018-10-02
申请号：US14717850
申请日：2015-05-20
Applicant: ARM Limited
Inventor： Edward Plowman , Sean Ellis
Abstract: When rendering a region of a three-dimensional object represented by a base set of polygon vertices in a graphics processing pipeline, a first processing stage uses meta-information representative of the surface relief of the region of the three-dimensional object to determine whether to generate a set of additional polygon vertices over the region of the three-dimensional object, and generates the additional set of polygon vertices (when this is deemed necessary). A second processing stage then uses information representative of the surface relief of the region of the three-dimensional object to modify the positions of one or more of the polygon vertices, before the vertices are assembled into primitives that are then rasterised and rendered.
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公开(公告)号：US20160042491A1
公开(公告)日：2016-02-11
申请号：US14822605
申请日：2015-08-10
Applicant: ARM Limited
Inventor： Daren Croxford , Ben James , Sean Ellis , Edward Charles Plowman
Abstract: A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer 15 by writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitry 14 arranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitry 16 arranged to acquire meta-data from the compressed block of data, and processing circuitry 21 arranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.
Abstract translation: 数据处理系统包括处理电路，其被配置为产生数据以形成数据的输出阵列，处理电路被布置为通过将代表输出数据阵列的特定区域的数据的压缩块写入到输出缓冲器15中而将其输出到输出 缓冲器，处理电路14，其被布置为从输出缓冲器读取表示数据阵列的特定区域的压缩数据块，布置成从压缩数据块获取元数据的处理电路16以及被布置成处理 数据块。 所获取的元数据用于影响数据块的处理。
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公开(公告)号：US09122646B2
公开(公告)日：2015-09-01
申请号：US13623744
申请日：2012-09-20
Applicant: ARM Limited
Inventor： Sean Ellis , Andreas Engh-halstvedt , Jorn Nystad
CPC classification number: G06F15/16 , G06F9/5083 , G06T1/20 , G06T11/40
Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.
Abstract translation: 在具有多个渲染处理器的基于瓦片的图形处理系统中，要处理以生成用于显示的输出帧30的瓦片组31在不同的渲染处理器之间通过定义相应的瓦片穿越路径32,33,34,35进行划分，用于 每个渲染处理器从最初分配给处理器的瓦片开始，并且至少对于沿着路径的初始瓦片，遍历输出中的空间相邻的瓦片，并且如果跟随到它们的结尾，则遍历要渲染的每个瓦片。 然后，将待处理的给定渲染处理器的下一个图块选择为沿其定义的路径的下一个图块，除非路径中的下一个图块已经被另一个渲染处理器处理（或已被处理），在这种情况下 将要分配给渲染处理器的下一个瓦片选择为该处理器的瓦片穿越路径中的另外的空闲瓦片。
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