SNOOP OPTIMIZATION FOR MULTI-PORTED NODES OF A DATA PROCESSING SYSTEM

    公开(公告)号:US20170185516A1

    公开(公告)日:2017-06-29

    申请号:US14980144

    申请日:2015-12-28

    Applicant: ARM Limited

    CPC classification number: G06F12/0831 G06F2212/1048

    Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

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