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    SNOOP OPTIMIZATION FOR MULTI-PORTED NODES OF A DATA PROCESSING SYSTEM
    1.
    发明申请
    SNOOP OPTIMIZATION FOR MULTI-PORTED NODES OF A DATA PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20170185516A1

    公开(公告)日：2017-06-29

    申请号：US14980144

    申请日：2015-12-28

    Applicant: ARM Limited

    Inventor： Ashley Miles STEVENS ,  Andrew David TUNE ,  Daniel Adam SARA

    IPC: G06F12/08 ,  G06F9/30 ,  G06F15/80 ,  G06F15/78

    CPC classification number: G06F12/0831 ,  G06F2212/1048

    Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

    SWITCHING DEVICE USING BUFFERING
    2.
    发明申请
    SWITCHING DEVICE USING BUFFERING 审中-公开

    公开(公告)号：US20170315947A1

    公开(公告)日：2017-11-02

    申请号：US15139559

    申请日：2016-04-27

    Applicant: ARM Limited

    Inventor： Ian David ANDREWS ,  Andrew David TUNE ,  Daniel Adam SARA ,  George Robert Scott LLOYD

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/4022 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

    TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY
    4.
    发明申请
    TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY 有权
    在互连电路中进行交易响应修改

    公开(公告)号：US20160103776A1

    公开(公告)日：2016-04-14

    申请号：US14874801

    申请日：2015-10-05

    Applicant: ARM LIMITED

    Inventor： Andrew David TUNE ,  Arthur Brian LAUGHTON ,  Daniel Adam SARA ,  Sean James SALISBURY ,  Peter Andrew RIOCREUX

    IPC: G06F13/364 ,  G06F15/78 ,  G06F13/42

    CPC classification number: G06F13/364 ,  G06F13/4282

    Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

    Abstract translation: 用于将交易主机4,6,8连接到交易从站12,14的互连电路10包括响应修改电路18.响应修改电路包括存储用于修改目标事务响应的标识的候选列表缓冲器电路28。 响应修改电路18使用该识别数据来识别传送中的事务响应流中的修改目标事务响应。 响应修改电路18然后用于形成被修改的事务响应，以代替对交易主机4,6,8的修改目标事务响应。

    INTERCONNECT AND METHOD OF OPERATION OF AN INTERCONNECT
    6.
    发明申请
    INTERCONNECT AND METHOD OF OPERATION OF AN INTERCONNECT 有权
    互连的互连和操作方法

    公开(公告)号：US20160203093A1

    公开(公告)日：2016-07-14

    申请号：US14959170

    申请日：2015-12-04

    Applicant: ARM LIMITED

    Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Sean James SALISBURY ,  Daniel Adam SARA ,  George Robert Scott LLOYD

    IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

    Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

    Abstract translation: 提供了用于连接多个主设备和多个从设备的互连的互连和操作方法。 危险管理电路用于将交易序列化到重叠地址。 另外，门控电路确保在与一个或多个主设备的接口上的有序写入观察（OWO）行为，门控电路接收写入事务的写入地址传输，并且执行门控操作以将写入地址传输的门向前传播到 从设备为了确保OWO的行为。 门控电路在危害管理电路的控制下执行门控操作。 因此，对于由危险管理电路进行危险检查的写入事务，这样就不需要实施任何其他进程来专门管理这些写入事务的OWO行为。

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