公开(公告)号：US12079471B2

公开(公告)日：2024-09-03

申请号：US17875457

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/084 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

公开(公告)号：US12072798B2

公开(公告)日：2024-08-27

申请号：US17378690

申请日：2021-07-17

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Philip Shilane ,  Kimberly Lu ,  Joseph Brandt ,  Nicholas Noto ,  Tipper Truong ,  Mariah Arevalo

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/154

Abstract: Systems and methods for cleaning a storage system. A deduplicated storage system is cleaned by identifying structures that include dead or unreferenced segments. This includes processing recipes to identify the segments that are no longer part of a live object recipe. Then, the dead segments are removed. This is accomplished by copying forward the live segments and then deleting, as a whole, the structure that included the dead segments.

公开(公告)号：US11966337B2

公开(公告)日：2024-04-23

申请号：US18115856

申请日：2023-03-01

Applicant: ROKU, INC.

Inventor： Bill Ataras

IPC: G06F16/957 ,  G06F8/65 ,  G06F8/656 ,  G06F12/084 ,  G06F12/0873

CPC classification number: G06F12/084 ,  G06F8/65 ,  G06F8/656 ,  G06F12/0873 ,  G06F16/9574 ,  G06F2212/1008 ,  G06F2212/1048 ,  G06F2212/163 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/314 ,  G06F2212/62

Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a data item key corresponding to a request from a user profile operating on a media player and receiving a version identifier corresponding to a first version of an application operating on the media player. It is determined that a shared cache includes a first value and second value for the data item key. A key component is generated corresponding to the user profile. Both the generated key component and the data item key are provided to the shared cache, and the first value of the data item as stored in the shared cache is received. The first value of the first version of the data item is updated.

公开(公告)号：US11797181B2

公开(公告)日：2023-10-24

申请号：US17170280

申请日：2021-02-08

Applicant: Kove IP, LLC

Inventor： Timothy A. Stabrawa ,  Zachary A. Cornelius ,  John Overton ,  Andrew S. Poling ,  Jesse I. Taylor

IPC: G06F3/06 ,  H04L67/1097 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F3/0607 ,  G06F3/0604 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/08 ,  H04L67/1097 ,  G06F12/10 ,  G06F2212/1048 ,  Y02D10/00

Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.

公开(公告)号：US11755203B2

公开(公告)日：2023-09-12

申请号：US17589648

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US11720248B2

公开(公告)日：2023-08-08

申请号：US17715022

申请日：2022-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

公开(公告)号：US20230214380A1

公开(公告)日：2023-07-06

申请号：US18118440

申请日：2023-03-07

Applicant: Chia Network Inc.

Inventor： Bram Cohen ,  Krzysztof Pietrzak ,  Mariano Sorgente

IPC: G06F16/23 ,  G06F12/02 ,  H04L9/32

CPC classification number: G06F16/2379 ,  G06F12/0223 ,  H04L9/3239 ,  G06F2212/1048 ,  H04L9/50

Abstract: A method for extending a blockchain comprises, at a space server: allocating an amount of drive storage for generating proofs-of-space; or accessing a first challenge based on a prior block of the blockchain, the prior block comprising a first proof-of-space and a first proof-of-time; in response to accessing the first challenge, generating a second proof-of-space based on the first challenge and the amount of drive storage, the second proof-of-space indicating allocation of the amount of drive storage; accessing a second proof-of-time based on the prior block and indicating a first time delay elapsed after extension of the blockchain with the prior block; generating a new block comprising the second proof-of-space and the second proof-of-time; and broadcasting the new block over a distributed network.

公开(公告)号：US20230153239A1

公开(公告)日：2023-05-18

申请号：US17952537

申请日：2022-09-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ji Wook YOUN ,  Jongtae SONG ,  Kyeong-Eun HAN

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F2212/1048

Abstract: A method and apparatus for allocating a memory address in a resource-centric network are disclosed. The method of allocating a memory address may include receiving a request for a new service, determining whether the new service is able to be accommodated in a virtual memory that is pre-allocated in a resource-centric network, when the new service is able to be accommodated, allocating a memory area for accommodating the new service to the virtual memory, and when the new service is not able to be accommodated, allocating the memory area by using an additionally allocated area of a virtual memory of the resource-centric network.

公开(公告)号：US11650928B2

公开(公告)日：2023-05-16

申请号：US17715734

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0895 ,  G06F12/126 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06F12/0895 ,  G06F12/023 ,  G06F12/126 ,  G06T1/60 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/608

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

公开(公告)号：US20190243779A1

公开(公告)日：2019-08-08

申请号：US15891174

申请日：2018-02-07

Applicant: Alibaba Group Holding Limited

Inventor： Shu Li

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/1048 ,  G06F2212/2022 ,  G06F2212/684

Abstract: One embodiment facilitates operation of non-volatile memory. During operation, the system determines, by a flash translation layer module, a physical block address associated with a first request which indicates data to be read, wherein the non-volatile memory is divided into separate physical zones, wherein the physical block address is associated with a first physical zone, and each separate physical zone has a dedicated application to read or write data thereto. The system obtains a free page frame in a volatile memory by writing data from a cold page in the volatile memory to a second physical zone, wherein a cold page is a page with a history of access which is less than a predetermined threshold. The system loads, based on the physical block address, data from the non-volatile memory to the free page frame. The system executes the request based on the data loaded into the free page frame.