公开(公告)号：US10359831B2

公开(公告)日：2019-07-23

申请号：US15447866

申请日：2017-03-02

Applicant: ARM Limited

Inventor： Ashley John Crawford ,  Andrew Christopher Rose ,  Tessil Thomas ,  David Guillen Fandos

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.