中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.012 seconds)

    Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory
    2.
    发明授权
    Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory 有权

    公开(公告)号：US11314658B2

    公开(公告)日：2022-04-26

    申请号：US15574596

    申请日：2016-04-28

    Applicant: ARM LIMITED

    Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

    IPC: G06F12/1036 ,  G06F12/02 ,  G06F12/14 ,  G06F12/10 ,  G06F9/455 ,  G06F12/1009

    Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

    Cache power management
    3.
    发明授权
    Cache power management 有权

    公开(公告)号：US10359831B2

    公开(公告)日：2019-07-23

    申请号：US15447866

    申请日：2017-03-02

    Applicant: ARM Limited

    Inventor： Ashley John Crawford ,  Andrew Christopher Rose ,  Tessil Thomas ,  David Guillen Fandos

    IPC: G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

    Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

    Communication of message signalled interrupts
    4.
    发明授权
    Communication of message signalled interrupts 有权
    消息信号中断的通信

    公开(公告)号：US08924615B2

    公开(公告)日：2014-12-30

    申请号：US13661456

    申请日：2012-10-26

    Applicant: ARM Limited

    Inventor： Richard Roy Grisenthwaite ,  Anthony Jebson ,  Andrew Christopher Rose ,  Matthew Lucien Evans

    IPC: G06F13/26 ,  G06F13/24

    CPC classification number: G06F13/26 ,  G06F13/24

    Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

    Abstract translation: 提供全局中断号码空间38用于消息信号中断。 中断目的地10,12,14,16提供有等待中断高速缓存24，其中由全局挂起状态存储器34提供的后备存储器由全部高速缓存或独立的各个未决状态存储器56共享。中断号码空间可以被划分为具有 可编程映射数据用于指示哪些中断目的地负责哪些区域。 当中断从一个中断目的地迁移到另一个中断时，这种可编程映射数据被更新。 在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

    Secure initialisation
    5.
    发明授权
    Secure initialisation 有权

    公开(公告)号：US10558590B2

    公开(公告)日：2020-02-11

    申请号：US15574938

    申请日：2016-04-26

    Applicant: ARM LIMITED

    Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose ,  Matthew Lucien Evans

    IPC: G06F12/14 ,  G06F12/06

    Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

    APPARATUS AND METHOD FOR HANDLING WRITE OPERATIONS
    6.
    发明申请
    APPARATUS AND METHOD FOR HANDLING WRITE OPERATIONS 审中-公开

    公开(公告)号：US20190171573A1

    公开(公告)日：2019-06-06

    申请号：US15831609

    申请日：2017-12-05

    Applicant: Arm Limited

    Inventor： Andrew Christopher Rose ,  Richard Roy Grisenthwaite ,  Ali Ghassan Saidi

    IPC: G06F12/0891 ,  G06F12/126 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38

    Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.

    Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level
    8.
    发明授权
    Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level 有权

    公开(公告)号：US10802729B2

    公开(公告)日：2020-10-13

    申请号：US15574549

    申请日：2016-04-26

    Applicant: ARM LIMITED

    Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

    IPC: G06F3/06 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/14

    Abstract: A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.

    Enforcing data protection in an interconnect
    9.
    发明授权
    Enforcing data protection in an interconnect 有权

    公开(公告)号：US10078589B2

    公开(公告)日：2018-09-18

    申请号：US14700259

    申请日：2015-04-30

    Applicant: ARM LIMITED

    Inventor： Daniel Sara ,  Antony John Harris ,  Håkan Lars-Göran Persson ,  Andrew Christopher Rose ,  Ian Bratt

    IPC: G06F12/08 ,  G06F12/14 ,  G06F12/0831

    CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F12/1491 ,  G06F2212/1052

    Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

Patent Agency Ranking