公开(公告)号：US20210026554A1

公开(公告)日：2021-01-28

申请号：US16521723

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Andrew John TURNER ,  Alex James WAUGH ,  Geoffray LACOURBA ,  Fergus Wilson MACGARRY

IPC: G06F3/06

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

公开(公告)号：US20170371560A1

公开(公告)日：2017-12-28

申请号：US15593560

申请日：2017-05-12

Applicant: ARM Limited

Inventor： Fergus Wilson MACGARRY ,  Michael Andrew CAMPBELL

IPC: G06F3/06

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed. During the training operation, none of the pending access requests will be issued to the memory device, and accordingly by performing the maintenance operation during this period, the potential impact that the performance of the maintenance operation could have had on the handling of the access requests is avoided.

公开(公告)号：US20200089549A1

公开(公告)日：2020-03-19

申请号：US16135335

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Fergus Wilson MACGARRY ,  Alex James WAUGH

IPC: G06F9/54 ,  G06F11/34

Abstract: A first event source generates a first indication of a first event which has occurred in the first event source, the first indication being one of a predefined set of indications corresponding to a plurality of event types. A second event source generates a second indication of a second event which has occurred in the second event source, the second indication being one of the predefined set of indications corresponding to the plurality of event types. First event selection circuitry responds to the first indication matching a selected event type of the plurality of event types to generate a first count signal and second event selection circuitry responds to the second indication matching the selected event type of the plurality of event types to generate a second count signal. Count circuitry increments a counter in response to either the first count signal or the second count signal.