公开(公告)号：US20230396550A1

公开(公告)日：2023-12-07

申请号：US17829888

申请日：2022-06-01

Applicant: Arm Limited

Inventor： Andrew John TURNER ,  Shobhit SINGHAL ,  Alex James WAUGH ,  Inaki Abadia OSTA

IPC: H04L47/20 ,  H04L47/25 ,  H04L47/78

CPC classification number: H04L47/20 ,  H04L47/25 ,  H04L47/781

Abstract: Interconnect systems and method of operating such are disclosed. A plurality of nodes coupled via a packet transport path form an interconnect and the nodes provide ingress points to the interconnect for a plurality of packet sources. A central controller holds permitted rate indications for each of the plurality of packet sources, in accordance with which each packet source sends packets via the interconnect. The nodes each respond to packet collision event at that node by sending a collision report to the central controller. In response the central controller, in respect of a collision pair of packet sources associated with the packet collision, decreases the permitted rate indication corresponding to a packet source of the collision pair of packet sources which currently has the higher permitted rate indication. Periodically the permitted rate indications of all of the packet sources are increased, subject to a maximum permitted rate indication for each.

公开(公告)号：US20210026554A1

公开(公告)日：2021-01-28

申请号：US16521723

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Andrew John TURNER ,  Alex James WAUGH ,  Geoffray LACOURBA ,  Fergus Wilson MACGARRY

IPC: G06F3/06

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

公开(公告)号：US20140351471A1

公开(公告)日：2014-11-27

申请号：US13898816

申请日：2013-05-21

Applicant: ARM LIMITED

Inventor： Anthony JEBSON ,  Andrew John TURNER ,  Matthew Lucien EVANS ,  Gareth James EVANS ,  Adam James MCNEENEY

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Abstract translation: 一种中断控制器，用于控制在包括至少一个物理处理单元的数据处理装置处接收的中断的路由和处理，所述物理处理单元被配置为运行多个虚拟处理器和存储器中的至少一个。 中断控制器包括具有与单元对应的至少一个数据存储器的再分配电路，数据存储器存储指向虚拟挂起表的指针，该虚拟挂起表存储当前在相应单元上运行的虚拟处理器的当前待处理的虚拟中断，以及指向待处理表的指针 被配置为存储用于相应单元的当前待处理的物理中断，以及被配置为接收用于中断虚拟处理器的虚拟中断的输入。 控制电路被配置为将虚拟中断添加到虚拟挂起表并将虚拟中断存储在存储在存储器中的虚拟处理器的虚拟挂起表中。

公开(公告)号：US20210271512A1

公开(公告)日：2021-09-02

申请号：US17056896

申请日：2019-05-01

Applicant: Arm Limited

Inventor： Timothy Nicholas HAY ,  Martin WEIDMANN ,  Michael Alexander KENNEDY ,  Andrew John TURNER

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F9/455

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

公开(公告)号：US20200327062A1

公开(公告)日：2020-10-15

申请号：US16382394

申请日：2019-04-12

Applicant: Arm Limited

Inventor： Geoffray Matthieu LACOURBA ,  Andrew John TURNER ,  Alex James WAUGH

IPC: G06F12/0868 ,  G06F13/38 ,  G06F13/14

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

公开(公告)号：US20230418766A1

公开(公告)日：2023-12-28

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Jamshed JALAL ,  Dimitrios KASERIDIS ,  Gurunath RAMAGIRI ,  Ho-Seop KIM ,  Andrew John TURNER ,  Rania Hussein Hassan MAMEESH

IPC: G06F12/126 ,  G06F12/0811

CPC classification number: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

公开(公告)号：US20210103524A1

公开(公告)日：2021-04-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Andrew John TURNER

IPC: G06F12/0815 ,  G06F9/52

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US20200293233A1

公开(公告)日：2020-09-17

申请号：US16353257

申请日：2019-03-14

Applicant: Arm Limited

Inventor： Alex James WAUGH ,  Geoffray Mattheiu LACOURBA ,  Andrew John TURNER ,  Sergio SCHULER

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/0837 ,  G06F9/50

Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.