公开(公告)号：US20170031713A1

公开(公告)日：2017-02-02

申请号：US15194928

申请日：2016-06-28

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL ,  Fergus Wilson MacGARRY ,  Bruce James MATHEWSON

IPC: G06F9/48

Abstract: There is provided an apparatus comprising scheduling circuitry, which selects a task as a selected task to be performed from a plurality of queued tasks, each having an associated priority, in dependence on the associated priority of each queued task. Escalating circuitry increases the associated priority of each of the plurality of queued tasks after a period of time. The plurality of queued tasks comprises a time-sensitive task having an associated deadline and in response to the associated deadline being reached, the scheduling circuitry selects the time-sensitive task as the selected task to be performed.

Abstract translation: 提供了一种装置，其包括调度电路，其根据每个排队的任务的相关优先级，从多个排队的任务中选择任务作为要执行的每个具有关联优先级的任务。 升级电路在一段时间之后增加多个排队任务中的​​每一个的相关优先级。 多个排队任务包括具有相关期限的时间敏感任务，并且响应于到达的相关期限，调度电路选择时间敏感任务作为要执行的所选择的任务。

公开(公告)号：US20140317360A1

公开(公告)日：2014-10-23

申请号：US13868180

申请日：2013-04-23

Applicant: ARM Limited

Inventor： Michael Andrew CAMPBELL

IPC: G06F15/167

CPC classification number: G06F15/167 ,  G06F12/0207 ,  G06F12/0623 ,  G06F13/1615

Abstract: Memory access circuitry for controlling access to a memory comprising multiple memory units arranged in parallel with each other. The memory access circuitry comprising: two access units each configured to select one of the multiple memory units in response to a received memory access request and to control and track subsequent accesses to the selected memory unit, the multiple memory units comprising at least three memory units; arbitration circuitry configured to receive the memory access requests from a system and to select and forward the memory access requests to one of the two access units, the arbitration circuitry being configured to forward a plurality of memory access requests for accessing one memory unit to a first of the two access units, and to direct a plurality of memory access requests for accessing a further memory unit to a second of the two access units and to subsequently direct a plurality of memory access requests for accessing a yet further memory unit to one of the first or second access units. The two access units comprise storing circuitry to store requests in a queue prior to transmitting the requests to the respective memory unit; and tracking circuitry to track requests sent to the respective memory units and to determine when to transmit subsequent requests from the queue. The control circuitry is configured to set a state of each of the two access units, the state being one of active, prepare and dormant, the access unit in the active state being operable to transmit both access and activate requests to the respective memory unit, the activate request preparing the access in the respective memory unit and the access request accessing the data, the access unit in the prepare state being operable to transmit the activate requests and not the access requests, the access unit in the dormant state being operable not to transmit any access or activate requests, the control circuitry being configured to switch states of the two access units periodically and to set not more than one of the access units to the active state at a same time.

公开(公告)号：US20140229766A1

公开(公告)日：2014-08-14

申请号：US13764050

申请日：2013-02-11

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL

IPC: G06F11/10

CPC classification number: G06F11/3037 ,  G06F11/106

Abstract: An apparatus and method are provided for opportunistically performing scrubbing operations on a memory device. The apparatus is used for accessing the memory device in response to access requests issued by at least one requesting device and comprises interface circuitry that is configured to access the memory device in response to the access requests. The apparatus also comprises activity monitoring circuitry which generates memory access activity data that results from memory access activity between the interface circuitry and the memory device. Scrubbing circuitry is also included and is configured to issue scrubbing access requests to perform the scrubbing operations, the scrubbing access requests being issued in response to the memory access activity data indicating a trigger condition. The above apparatus allows scrubbing access requests to be issued taking into account actual memory access activity between the interface circuitry and the memory device, thereby allowing the access requests to be issued opportunistically in such a way that the performance cost/system power consumption necessary to achieve a particular reliability can be reduced compared to known techniques.

Abstract translation: 提供了一种用于机会地对存储器件进行擦洗操作的装置和方法。 所述设备用于响应于由至少一个请求设备发出的访问请求来访问存储设备，并且包括被配置为响应于访问请求访问存储设备的接口电路。 该装置还包括活动监视电路，其生成由接口电路和存储设备之间的存储器访问活动产生的存储器访问活动数据。 还包括擦洗电路，并且被配置为发出擦洗访问请求以执行擦洗操作，响应于指示触发条件的存储器访问活动数据发出擦洗访问请求。 上述装置允许考虑接口电路和存储器件之间的实际存储器访问活动来擦除访问请求，从而允许机会地发出访问请求，使得实现所需的性能成本/系统功耗 与已知技术相比，可以降低特定的可靠性。

公开(公告)号：US20230161705A1

公开(公告)日：2023-05-25

申请号：US17532555

申请日：2021-11-22

Applicant: Arm Limited

Inventor： Graeme Leslie INGRAM ,  Michael Andrew CAMPBELL

IPC: G06F12/0871 ,  G06F12/0877 ,  G06F12/0808 ,  G06F12/02

CPC classification number: G06F12/0871 ,  G06F12/0877 ,  G06F12/0808 ,  G06F12/0246

Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

公开(公告)号：US20210103493A1

公开(公告)日：2021-04-08

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Michael Andrew CAMPBELL ,  Alexander Alfred HORNUNG ,  Alex James WAUGH ,  Klas Magnus BRUCE ,  Richard Roy GRISENTHWAITE

IPC: G06F11/10 ,  G06F11/30 ,  G11C29/18

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US20180143771A1

公开(公告)日：2018-05-24

申请号：US15358885

申请日：2016-11-22

Applicant: ARM Limited

Inventor： Kshitij SUDAN ,  Stephan DIESTELHORST ,  Michael Andrew CAMPBELL

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.

公开(公告)号：US20140229793A1

公开(公告)日：2014-08-14

申请号：US13764003

申请日：2013-02-11

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL ,  Thomas Kelshaw CONWAY

IPC: G06F11/10

CPC classification number: G06F11/1012 ,  G06F11/1048

Abstract: An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction. The decoding circuitry comprises error correction circuitry configured, for each read code word, to perform an error correction process to detect and correct errors in up to P symbols of the code word, where P is dependent on the number of ECC symbols in the code word. Error tracking circuitry determines error quantity indication data indicative of the errors detected by the error correction circuitry, and in response to the error quantity indication data indicating that an error threshold condition has been reached, the apparatus transitions from a normal mode of operation to a safety mode of operation.

Abstract translation: 一种装置包括编码电路以产生用于存储在存储器件中的代码字。 解码电路响应于读取事务来解码从存储器件读取的一个或多个代码字，以便产生用于响应于读取事务而输出的读取数据。 解码电路包括纠错电路，为每个读码字配置，执行纠错处理以检测和纠正代码字最多P个符号的错误，其中P取决于代码字中的ECC符号的数目 。 错误跟踪电路确定指示由纠错电路检测到的错误的错误量指示数据，并且响应于指示已经达到错误阈值条件的错误量指示数据，装置从正常操作模式转换到安全 操作模式。

公开(公告)号：US20220374154A1

公开(公告)日：2022-11-24

申请号：US17755507

申请日：2020-09-01

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL ,  Matteo Maria ANDREOZZI ,  Lorenzo BIAGINI ,  Giovanni STEA ,  Ankit MEHTA

IPC: G06F3/06

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.

公开(公告)号：US20200089634A1

公开(公告)日：2020-03-19

申请号：US16135149

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Tushar P. RINGE ,  Anitha KONA ,  Andrew Brookfield SWAINE ,  Michael Andrew CAMPBELL

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/364

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device. The slave device has transfer identifier generation circuitry for generating, for each data transfer, a transfer identifier to be transmitted over the connection medium to identify which data item in the plurality of data items is being transferred by that data transfer. The master device has buffer circuitry to buffer data items received by the plurality of data transfers, and to employ the transfer identifier provided for each data transfer to cause the plurality of data items to be provided to the processing circuitry in a determined order irrespective of an order in which the data items are transferred to the master device via the plurality of data transfers. This can significantly reduce the overhead required to manage the supply of the data items to the processing circuitry in the required determined order.

公开(公告)号：US20180089079A1

公开(公告)日：2018-03-29

申请号：US15273743

申请日：2016-09-23

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Wendy Arnott ELSASSER ,  Michael Andrew CAMPBELL

IPC: G06F12/06 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0888

CPC classification number: G06F12/0623 ,  G06F12/084 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/4234 ,  G06F2212/6046 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.