公开(公告)号：US20170153975A1

公开(公告)日：2017-06-01

申请号：US14953093

申请日：2015-11-27

Applicant: ARM Limited

Inventor： Gregory Andrew CHADWICK ,  Adnan KHAN

IPC: G06F12/08

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/1054 ,  G06F2212/1024 ,  G06F2212/1032

Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line. Partial linefill notification circuitry is used to provide partial linefill information to the atomic update handling circuitry during the linefill operation, and the atomic update handling circuitry is arranged to initiate the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line. This can provide a performance benefit, by avoiding the need for the atomic update handling circuitry to await completion of the linefill operation before beginning the atomic update operation.

公开(公告)号：US20210157730A1

公开(公告)日：2021-05-27

申请号：US16690506

申请日：2019-11-21

Applicant: Arm Limited

Inventor： Alexander Alfred HORNUNG ,  Jose GONZALEZ-GONZALEZ ,  Gregory Andrew CHADWICK

IPC: G06F12/0862

Abstract: An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.