公开(公告)号：US09646160B2

公开(公告)日：2017-05-09

申请号：US14479688

申请日：2014-09-08

Applicant: ARM LIMITED

Inventor： Yohann Fred Arifidy Rabefarihy ,  Carlo Dario Fanara ,  Stephane Zonza ,  Jean-Baptiste Brelot

IPC: G06F21/00 ,  G06F21/60 ,  G06F21/55

CPC classification number: G06F21/60 ,  G06F21/755 ,  G06F21/81

Abstract: An apparatus and method are provided for enhancing resilience to attacks on reset of the apparatus. The apparatus comprises at least one storage element, and update circuitry that is configured to receive obscuring data, and which is responsive to a reset event to store in each of the at least one storage element a data value that is dependent on the current value of the obscuring data. For each such storage element, this ensures that the data value stored in that storage element is unpredictable following each reset event, thereby preventing the reproducibility of certain steps that would typically be taken by an attacker during an attack on the apparatus.

公开(公告)号：US09645824B2

公开(公告)日：2017-05-09

申请号：US13664659

申请日：2012-10-31

Applicant: ARM Limited

Inventor： Vladimir Vasekin ,  Allan John Skillman ,  Chiloda Ashan Senerath Pathirane ,  Jean-Baptiste Brelot

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.