公开(公告)号：US11074080B2

公开(公告)日：2021-07-27

申请号：US16864223

申请日：2020-05-01

Applicant: ARM Limited

Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

公开(公告)号：US11226828B2

公开(公告)日：2022-01-18

申请号：US16376058

申请日：2019-04-05

Applicant: Arm Limited

Inventor： Peter Vrabel ,  Allan John Skillman

IPC: G06F9/4401 ,  G06F1/08 ,  G06F9/48 ,  G06F1/3296

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

公开(公告)号：US09665494B2

公开(公告)日：2017-05-30

申请号：US14709784

申请日：2015-05-12

Applicant: ARM LIMITED

Inventor： Allan John Skillman ,  Chiloda Ashan Senerath Pathirane

IPC: G06F12/08 ,  G06F12/0884 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/121

CPC classification number: G06F12/0884 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/121 ,  G06F2212/1028 ,  G06F2212/604 ,  Y02D10/13

Abstract: A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.

公开(公告)号：US10705587B2

公开(公告)日：2020-07-07

申请号：US15133329

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/30 ,  G06F1/3234 ,  G06F1/3237

Abstract: Apparatus for processing data is provided with fetch circuitry for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry has a first operating mode and a second operating mode. Mode switching circuitry switches the pipeline circuitry, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline for performing out-of-order processing.

公开(公告)号：US09658919B2

公开(公告)日：2017-05-23

申请号：US14685779

申请日：2015-04-14

Applicant: ARM LIMITED

Inventor： Chiloda Ashan Senerath Pathirane ,  Allan John Skillman

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/08

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/079 ,  G06F11/08 ,  G06F11/1016 ,  G06F11/1044

Abstract: A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.

公开(公告)号：US10402203B2

公开(公告)日：2019-09-03

申请号：US15578477

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behavior to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).

公开(公告)号：US09952871B2

公开(公告)日：2018-04-24

申请号：US14731789

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Simon John Craske ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3889

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

公开(公告)号：US09710359B2

公开(公告)日：2017-07-18

申请号：US14685799

申请日：2015-04-14

Applicant: ARM LIMITED

Inventor： Chiloda Ashan Senerath Pathirane ,  Allan John Skillman

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3648 ,  G06F11/3664

Abstract: A target apparatus 2 for debug includes a processing pipeline 18 for executing a sequence of program instructions. A debug interface 26 receives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction buffer 24 stores both the debug program instructions and non-debug program instructions. An arbiter 30 selects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory system 4, 6, 8, 10, 12, 14, 32 is shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.

公开(公告)号：US11579879B2

公开(公告)日：2023-02-14

申请号：US17224248

申请日：2021-04-07

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F12/1027

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US20210224071A1

公开(公告)日：2021-07-22

申请号：US17224248

申请日：2021-04-07

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.