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公开(公告)号：US09665494B2
公开(公告)日：2017-05-30
申请号：US14709784
申请日：2015-05-12
Applicant: ARM LIMITED
Inventor： Allan John Skillman , Chiloda Ashan Senerath Pathirane
IPC: G06F12/08 , G06F12/0884 , G06F12/0846 , G06F12/0864 , G06F12/0895 , G06F12/121
CPC classification number: G06F12/0884 , G06F12/0846 , G06F12/0864 , G06F12/0895 , G06F12/121 , G06F2212/1028 , G06F2212/604 , Y02D10/13
Abstract: A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.
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Patent Agency Ranking
2.发明授权公开(公告)号：US10579389B2
公开(公告)日：2020-03-03
申请号：US14929904
申请日：2015-11-02
Applicant: ARM Limited
Abstract: An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group.
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公开(公告)号：US09710359B2
公开(公告)日：2017-07-18
申请号：US14685799
申请日：2015-04-14
Applicant: ARM LIMITED
Inventor： Chiloda Ashan Senerath Pathirane , Allan John Skillman
CPC classification number: G06F11/3636 , G06F11/3648 , G06F11/3664
Abstract: A target apparatus 2 for debug includes a processing pipeline 18 for executing a sequence of program instructions. A debug interface 26 receives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction buffer 24 stores both the debug program instructions and non-debug program instructions. An arbiter 30 selects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory system 4, 6, 8, 10, 12, 14, 32 is shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.
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公开(公告)号：US09645824B2
公开(公告)日：2017-05-09
申请号：US13664659
申请日：2012-10-31
Applicant: ARM Limited
Inventor： Vladimir Vasekin , Allan John Skillman , Chiloda Ashan Senerath Pathirane , Jean-Baptiste Brelot
IPC: G06F9/38
CPC classification number: G06F9/3806
Abstract: An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.
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公开(公告)号：US09449717B2
公开(公告)日：2016-09-20
申请号：US14310162
申请日：2014-06-20
Applicant: ARM LIMITED
CPC classification number: G11C29/14 , G06F11/008 , G11C29/16 , G11C2029/0409
Abstract: A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.
Abstract translation: 数据处理装置具有至少一个存储器和处理电路。 存储器内置自检（MBIST）接口接收MBIST请求，指示要执行测试程序来测试至少一个目标存储器位置。 控制电路检测MBIST请求并保留用于测试至少一个保留的存储器位置，包括目标存储器位置。 在测试过程期间，存储器继续服务处理电路所发出的存储器事务，该处理电路针对除控制电路所保留的保留位置以外的存储位置。 如果处理电路尝试访问预留的存储器位置，则停止处理。 测试包括不经常发生的短突发事件。 这样，当处理器在现场运行时，MBIST测试可能会持续下去，从而降低性能影响。
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公开(公告)号：US09658919B2
公开(公告)日：2017-05-23
申请号：US14685779
申请日：2015-04-14
Applicant: ARM LIMITED
Inventor： Chiloda Ashan Senerath Pathirane , Allan John Skillman
CPC classification number: G06F11/0793 , G06F11/0751 , G06F11/0772 , G06F11/0784 , G06F11/079 , G06F11/08 , G06F11/1016 , G06F11/1044
Abstract: A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.
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