公开(公告)号：US20160283396A1

公开(公告)日：2016-09-29

申请号：US15076764

申请日：2016-03-22

Applicant: ARM Limited

Inventor： Vahan TER-GRIGORYAN ,  Hakan Lars-Goran PERSSON ,  Jesus Javier de los REYES DARIAS ,  Vinod Pisharath Hari PAI

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/507 ,  G06F2212/651 ,  G06F2212/681 ,  Y02D10/13

Abstract: A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation of one of the other intermediate memory addresses in the set.

Abstract translation: 多级存储器管理单元（MMU）包括被配置为将输入虚拟存储器地址转换为对应的中间存储器地址的第一MMU级，第一MMU级生成包括对应的中间存储器地址的两个或更多个中间存储器地址的集合; 以及第二MMU级，被配置为将由第一MMU级提供的中间存储器地址转换为物理存储器地址，第二MMU级响应于从第一MMU级接收的中间存储器地址提供两组或更多组 物理存储器地址，包括对应于从第一MMU级接收的中间存储器地址的物理存储器地址; 第一MMU级被配置为提供到第二MMU级用于转换，该集合中的中间存储器地址除了组中的任何中间存储器地址之外，第二MMU级将为其提供物理存储器地址作为对一个 的集合中的其他中间存储器地址。

公开(公告)号：US20160323407A1

公开(公告)日：2016-11-03

申请号：US15099244

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Jesus Javier de los REYES DARIAS ,  Hakan PERSSON ,  Roko GRUBISIC ,  Vinod Pisharath Hari PAI

IPC: H04L29/08 ,  H04L29/06

CPC classification number: H04L67/2842 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0891 ,  G06F2212/1024 ,  G06F2212/681 ,  G06F2212/683 ,  H04L12/184 ,  H04L12/1877 ,  H04L12/5691 ,  H04L49/90 ,  H04L69/14 ,  Y02D10/13 ,  Y02D50/30

Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

Abstract translation: 数据处理装置具有多个高速缓存和用于控制高速缓存的控制器。 控制器和高速缓存通过第一网络和第二网络进行通信。 第一个网络用于从控制器到特定的一个缓存的单播通信。 第二网络用于从控制器到两个或更多个高速缓存的多播通信的通信。