公开(公告)号：US10283089B2

公开(公告)日：2019-05-07

申请号：US14727016

申请日：2015-06-01

Applicant: ARM Limited

Inventor： Damian Modrzyk ,  Pawel Duc ,  Piotr Chrobak ,  Michal Bogusz ,  Daren Croxford

IPC: G09G5/36 ,  G09G5/14 ,  G09G5/393 ,  G09G5/12 ,  G09G5/00 ,  G09G5/395

Abstract: A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.

公开(公告)号：US11323678B2

公开(公告)日：2022-05-03

申请号：US14949640

申请日：2015-11-23

Applicant: ARM Limited

Inventor： Michal Bogusz ,  Piotr Chrobak ,  Damian Modrzyk

IPC: H04N9/75 ,  H04N5/272 ,  H04N5/232

Abstract: An apparatus for providing a foreground frame to be composited with a background frame in a chroma-keying arrangement, each of the foreground frame and the background frame comprising one or more regions that together form the respective frame. A detection module determines whether each frame region has a predetermined colour value and generates and stores chroma keying information based on the determination. Control circuitry then controls image processing to be performed on the region according to the stored chroma keying information.

公开(公告)号：US20170061577A1

公开(公告)日：2017-03-02

申请号：US15238873

申请日：2016-08-17

Applicant: ARM Limited

Inventor： Michal Bogusz ,  Erik Persson

IPC: G06T3/40

CPC classification number: G06T3/40 ,  G06T1/60

Abstract: A scaling apparatus for scaling data arrays, such as images, comprises first horizontal scaling stage circuitry operable to scale a data array input to the scaling apparatus in the horizontal direction, one or more line memories for storing horizontal lines for a data array, wherein the or each line memory is for storing a horizontal line of data for the data array, vertical scaling stage circuitry operable to read data stored in the one or more line memories and to scale the read data in the vertical direction, and second horizontal scaling stage circuitry operable to scale a data array in the horizontal direction.

Abstract translation: 用于缩放数据阵列（诸如图像）的缩放装置包括可操作以在水平方向上缩放输入到缩放设备的数据阵列的第一水平缩放级电路，用于存储用于数据阵列的水平线的一个或多个行存储器，其中， 或者每行存储器用于存储用于数据阵列的水平线数据，垂直缩放级电路可操作以读取存储在一个或多个行存储器中的数据，并在垂直方向上缩放读数据;以及第二水平缩放级电路 可操作以在水平方向上缩放数据阵列。

公开(公告)号：US20160156893A1

公开(公告)日：2016-06-02

申请号：US14949640

申请日：2015-11-23

Applicant: ARM Limited

Inventor： Michal Bogusz ,  Piotr Chrobak ,  Damian Modrzyk

IPC: H04N9/75 ,  H04N5/272

Abstract: An apparatus for providing a foreground frame to be composited with a background frame in a chroma-keying arrangement, each of the foreground frame and the background frame comprising one or more regions that together form the respective frame. A detection module determines whether each frame region has a predetermined colour value and generates and stores chroma keying information based on the determination. Control circuitry then controls image processing to be performed on the region according to the stored chroma keying information.

Abstract translation: 一种用于提供要与色键配置中的背景帧合成的前景帧的装置，前景帧和背景帧中的每一个包括一起形成相应帧的一个或多个区域。 检测模块确定每个帧区域是否具有预定的颜色值，并且基于该确定产生并存储色度键控信息。 然后，控制电路根据所存储的色度键控信息来控制对该区域进行的图像处理。

公开(公告)号：US10255659B2

公开(公告)日：2019-04-09

申请号：US15238873

申请日：2016-08-17

Applicant: ARM Limited

Inventor： Michal Bogusz ,  Erik Persson

IPC: G06T1/60 ,  G06T3/40

Abstract: A scaling apparatus for scaling data arrays, such as images, comprises first horizontal scaling stage circuitry operable to scale a data array input to the scaling apparatus in the horizontal direction, one or more line memories for storing horizontal lines for a data array, wherein the or each line memory is for storing a horizontal line of data for the data array, vertical scaling stage circuitry operable to read data stored in the one or more line memories and to scale the read data in the vertical direction, and second horizontal scaling stage circuitry operable to scale a data array in the horizontal direction.

公开(公告)号：US20150356953A1

公开(公告)日：2015-12-10

申请号：US14727016

申请日：2015-06-01

Applicant: ARM Limited

Inventor： Damian Modrzyk ,  Pawel Duc ,  Piotr Chrobak ,  Michal Bogusz ,  Daren Croxford

IPC: G09G5/36 ,  G09G5/00 ,  G09G5/12 ,  G09G5/14 ,  G09G5/393

CPC classification number: G09G5/363 ,  G09G5/003 ,  G09G5/006 ,  G09G5/12 ,  G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/0492 ,  G09G2340/12 ,  G09G2360/02 ,  G09G2360/06 ,  G09G2360/128 ,  G09G2360/18

Abstract: A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.

Abstract translation: 显示控制器包括可操作以读取至少一个输入表面的输入级20，可操作以组合多个输入表面以生成合成输出表面的合成台28，可操作以将合成输出表面提供给显示器进行显示的输出级30 缩放引擎31，其可操作以缩放由构图阶段28生成的合成输出表面;以及写出阶段32，其可操作以将合成和/或缩放的输出表面写入外部存储器。