公开(公告)号：US20190155978A1

公开(公告)日：2019-05-23

申请号：US16253075

申请日：2019-01-21

Applicant: Arm Limited

Inventor： Paul Christopher de Dood

IPC: G06F17/50

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

公开(公告)号：US10185796B2

公开(公告)日：2019-01-22

申请号：US15601707

申请日：2017-05-22

Applicant: ARM Limited

Inventor： Paul Christopher de Dood

IPC: G06F17/00 ,  G06F17/50

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

公开(公告)号：US10657215B2

公开(公告)日：2020-05-19

申请号：US16253075

申请日：2019-01-21

Applicant: Arm Limited

Inventor： Paul Christopher de Dood

IPC: G06F17/50

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

公开(公告)号：US09912338B1

公开(公告)日：2018-03-06

申请号：US15482456

申请日：2017-04-07

Applicant: ARM Limited

Inventor： James Dennis Dodrill ,  Paul Christopher de Dood

IPC: H03L7/00 ,  H03K3/356

CPC classification number: H03L7/00 ,  H03K3/0375 ,  H03K3/356113 ,  H03K5/135 ,  H03K2005/00286

Abstract: A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.

公开(公告)号：US20200242293A1

公开(公告)日：2020-07-30

申请号：US16851029

申请日：2020-04-16

Applicant: Arm Limited

Inventor： Paul Christopher de Dood

IPC: G06F30/39

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

公开(公告)号：US20170255734A1

公开(公告)日：2017-09-07

申请号：US15601707

申请日：2017-05-22

Applicant: ARM Limited

Inventor： Paul Christopher de Dood

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/02

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.