公开(公告)号：US20180173271A1

公开(公告)日：2018-06-21

申请号：US15735362

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Ramnath Bommu Subbiah SWAMY

IPC: G06F1/10 ,  G06F1/06 ,  G06F1/12

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F1/12

Abstract: An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. A plurality of interface storage circuits (flip-flops) (12, 14, 16, 18) are coupled to the clock mesh and receive the clock signal from the clock mesh to control storage therein. The interface storage circuits (54) may be of a form controlled by multiple clock signals, CP0, CP1. A signal value D may be captured into the storage circuit upon a rising edge of a first clock signal CP0 and launched from the storage circuit upon the rising edge of a second clock signal CP1.

公开(公告)号：US20150162918A1

公开(公告)日：2015-06-11

申请号：US14097963

申请日：2013-12-05

Applicant: ARM Limited

Inventor： Ramnath Bommu Subbiah SWAMY

IPC: H03L7/081 ,  H03L7/083

CPC classification number: H03K5/135

Abstract: An on-chip clock signal generation apparatus is provided which is configured to generate an output clock signal to be passed off-chip in association with an output data signal. The apparatus comprises: an input configured to receive an input clock signal and clock phase generation circuitry configured to generate a plurality of candidate clock signals in dependence on the input clock signal. The candidate clock signals are phase-shifted with respect to one another. Selection circuitry is configured to select and output one of the candidate clock signals as the output clock signal in dependence on at least one selection signal. All components of the apparatus are embodied as digital components.

Abstract translation: 提供一种片上时钟信号产生装置，其被配置为产生与输出数据信号相关联地被片外传送的输出时钟信号。 该装置包括：被配置为接收输入时钟信号和被配置为根据输入时钟信号产生多个候选时钟信号的时钟相位产生电路的输入。 候选时钟信号相对于彼此相移。 选择电路被配置为根据至少一个选择信号来选择和输出候选时钟信号之一作为输出时钟信号。 该装置的所有部件被实现为数字部件。

公开(公告)号：US20180309565A1

公开(公告)日：2018-10-25

申请号：US15493429

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Richard Andrew PATERSON ,  Simon CROSSLEY ,  Ramnath Bommu Subbiah SWAMY ,  Steven Douglas KRUEGER ,  Anitha KONA

IPC: H04L7/00 ,  H04L12/26

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.