公开(公告)号：US09141338B2

公开(公告)日：2015-09-22

申请号：US13678621

申请日：2012-11-16

Applicant: ARM Limited

Inventor： Sachin Satish Idgunji ,  Vikas Chandra

IPC: G06F7/58

CPC classification number: G06F7/588 ,  G06F7/582

Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.

Abstract translation: 主从锁存器形式的存储电路2包括用作位存储电路的从级6。 从动级6包括一个逆变器链，当在正常模式下操作时包括偶数个反相器10,12，并且当以随机数生成模式操作时，包括奇数个反相器10,12,14等作为自由 运行环形振荡器。 当从随机数生成模式切换回正常模式时，停止振荡，并从位值存储电路6输出稳定的伪随机比特值。