公开(公告)号：US20240320005A1

公开(公告)日：2024-09-26

申请号：US18125416

申请日：2023-03-23

Applicant: Arm Limited

Inventor： Jesse Garrett BEU ,  Thomas Christopher GROCUTT

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30098

Abstract: A data processing apparatus includes first vector registers and second vector registers, both dynamically spatially and dynamically temporally dividable. Decode circuitry receives one or more matrix multiplication instructions that indicate a set of first elements in the first vector registers and a set of second elements in the second vector registers, and in response to receiving the matrix multiplication instructions they generate a matrix multiplication operation. The matrix multiplication operation causes one or more execution units to perform a matrix multiplication of the set of first elements by the set of second elements and an average bit width of the first elements is different to an average bit width of the second elements.

公开(公告)号：US20210311997A1

公开(公告)日：2021-10-07

申请号：US17260109

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Thomas Christopher GROCUTT ,  François Christopher Jacques BOTMAN

IPC: G06F16/903 ,  G06F12/1009

Abstract: A control table (22) defines information for controlling a processing component (20) to perform an operation. The table (22) comprises entries each corresponding to avariable size region defined by a first limit address and one of a second limit address and size. A binary search procedure is provided for looking up the table, comprising a number of search window narrowing steps, each narrowing a current search window of candidate entries to a narrower search window comprising fewer entries, based on a comparison of a query address against the first limit address of a selected candidate entry of the current search window. The comparison is independent of the second limit address or size of the selected candidate entry. After the search window is narrowed to a single entry, the query address is compared with the second limit address or size of that single entry.

公开(公告)号：US20210224380A1

公开(公告)日：2021-07-22

申请号：US17269205

申请日：2019-09-03

Applicant: Arm Limited

Inventor： Thomas Christopher GROCUTT

IPC: G06F21/54 ,  G06F21/55 ,  G06F21/64 ,  G06F21/74 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus comprises: processing circuitry to perform data processing in one of a plurality of security domains including at least a secure domain and a less secure domain, and memory access checking circuitry to check whether a memory access is allowed depending on security attribute data indicating which domain is associated with a target address. In response to a given change of program flow from processing in the less secure domain to a target instruction having an address associated with the secure domain: a fault is triggered when the target instruction is an instruction other than a gateway instruction indicating a valid entry point to the secure domain. When the target instruction is said gateway instruction, a stack pointer verifying action is triggered to verify whether it is safe to use a selected stack pointer stored in a selected stack pointer register.

公开(公告)号：US20190050226A1

公开(公告)日：2019-02-14

申请号：US16079241

申请日：2017-03-17

Applicant: ARM LIMITED

Inventor： Thomas Christopher GROCUTT

IPC: G06F9/30

Abstract: An apparatus comprises processing circuitry (4) and an instruction decoder (6) which supports vector instructions for which multiple lanes of processing are performed on respective data elements of a vector value. In response to a vector predication instruction, the instruction decoder (6) controls the processing circuitry (4) to set control information based on the outcome of a number of element comparison operations each for determining whether a corresponding element passes or fails a test condition. The control information controls processing of a predetermined number of subsequent vector instructions after the vector predication instruction. The predetermined number is hard-wired or identified by the vector predication instruction. For one of the subsequent vector instructions, an operation for a given portion of a given lane of vector processing is masked based on the outcome indicated by the control information for a corresponding data element.

公开(公告)号：US20140373171A1

公开(公告)日：2014-12-18

申请号：US14220499

申请日：2014-03-20

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT

IPC: G06F21/00

CPC classification number: G06F21/74 ,  G06F21/71

Abstract: A processing apparatus 2 has a secure domain 90 and a less secure domain 80. Security protection hardware 40 performs security checking operations when the processing circuitry 2 calls between domains. A data store 6 stores several software libraries 100 and library management software 110. The library management software 110 selects at least one of the libraries 100 as an active library which is executable by the processing circuitry 4 and at least one other library 100 as inactive libraries which are not executable. In response to an access to an inactive library, the library management software 110 switches which library is active.

Abstract translation: 处理装置2具有安全域90和较不安全的域80.当处理电路2在域之间调用时，安全保护硬件40执行安全检查操作。 数据存储器6存储多个软件库100和库管理软件110.库管理软件110将库100中的至少一个选择为可由处理电路4和至少一个其他库100作为非活动库执行的活动库 哪些不可执行。 响应于对非活动库的访问，库管理软件110切换哪个库是活动的。

公开(公告)号：US20130205125A1

公开(公告)日：2013-08-08

申请号：US13680298

申请日：2012-11-19

Applicant: Arm Limited

Inventor： Thomas Christopher GROCUTT

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/461 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/034

Abstract: Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.

公开(公告)号：US20190310847A1

公开(公告)日：2019-10-10

申请号：US16081147

申请日：2017-02-22

Applicant: ARM LIMITED

Inventor： Thomas Christopher GROCUTT

IPC: G06F9/30

Abstract: First and second forms of a complex multiply instruction are provided for operating on first and second operand vectors comprising multiple data elements including at least one real data element for representing the real part of a complex number and at least one imaginary element for representing an imaginary part of the complex number. One of the first and second forms of the instruction targets at least one real element of the destination vector and the other targets at least one imaginary element. By executing one of each instruction, complex multiplications of the form (a+ib)*(c+id) can be calculated using relatively few instructions and with only two vector register read ports, enabling DSP algorithms such as FFTs to be calculated more efficiently using relatively low power hardware implementations.

公开(公告)号：US20190196825A1

公开(公告)日：2019-06-27

申请号：US16324239

申请日：2017-08-14

Applicant: ARM LIMITED

Inventor： Thomas Christopher GROCUTT ,  François Christopher Jacques BOTMAN

IPC: G06F9/30 ,  G06F17/16 ,  G06F7/544

CPC classification number: G06F9/30036 ,  G06F7/5443 ,  G06F17/16

Abstract: An apparatus comprises processing circuitry, a number of vector register and a number of scalar registers. An instruction decoder is provided which supports decoding of a vector multiply-add instruction specifying at least one vector register and at least one scalar register. In response to the vector multiply-add instruction, the decoder controls the processing circuitry to perform a vector multiply-add instruction in which each lane of processing generates a respective result data element corresponding to a sum of difference of a product value and an addend value, with the product value comprising the product of a respective data element of a first vector value and a multiplier value. In each lane of processing at least one of the multiplier value and the addend value is specified as a portion of a scalar value stored in a scalar register.

公开(公告)号：US20170277537A1

公开(公告)日：2017-09-28

申请号：US15078149

申请日：2016-03-23

Applicant: ARM LIMITED

Inventor： Thomas Christopher GROCUTT

IPC: G06F9/30 ,  G06F15/82

CPC classification number: G06F9/30036 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30192 ,  G06F9/327 ,  G06F9/3836 ,  G06F9/3861 ,  G06F15/8053 ,  G06F15/82

Abstract: Processing circuitry supports overlapped execution of vector instructions when at least one beat of a first vector instruction is performed in parallel with at least one beat of a second vector instruction. The processing circuitry also supports mixed-scalar-vector instructions for which one of a destination register and one or more source registers is a vector register and another is a scalar register. In a sequence including first and subsequent mixed-scalar-vector instructions, instances of relaxed execution which can potentially lead to uncertain and incorrect results are permitted by the processing circuitry when the instructions are separated by fewer than a predetermined number of intervening instructions. In practice the situations which lead to the uncertain results are very rare and so it is not justified providing relatively expensive dependency checking circuitry for eliminating such cases.

公开(公告)号：US20150317474A1

公开(公告)日：2015-11-05

申请号：US14795933

申请日：2015-07-10

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT

IPC: G06F21/52 ,  G06F9/48 ,  G06F9/46 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/461 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/034

Abstract: Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.

Abstract translation: 处理电路可以在安全域和较不安全的域中操作。 响应于由处理电路执行的后台处理的初始异常，在触发异常处理例程之前由异常控制电路执行来自寄存器的第一子集的数据的状态保存，而异常处理例程有责任执行状态保存 数据来自第二个寄存器子集。 响应于第一个异常导致来自不安全域的安全域的转移，其中后台处理在较不安全的域中，异常控制电路在触发异常之前执行来自第二组寄存器的附加状态保存数据 处理程序。 为了响应引起从安全域到不太安全域的过渡的尾部链接异常，在不执行附加状态保存的情况下触发异常处理例程。