公开(公告)号：US10678506B2

公开(公告)日：2020-06-09

申请号：US15665715

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Alejandro Martinez Vicente ,  Jesse Garrett Beu ,  Mbou Eyole ,  Timothy Hayes

IPC: G06F9/30 ,  G06F7/02

Abstract: An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.

公开(公告)号：US12182261B2

公开(公告)日：2024-12-31

申请号：US17310008

申请日：2019-10-25

Applicant: Arm Limited

Inventor： Alastair David Reid ,  Albin Pierrick Tonnerre ,  Frederic Claude Marie Piry ,  Peter Richard Greenhalgh ,  Ian Michael Caulfield ,  Timothy Hayes ,  Giacomo Gabrielli

IPC: G06F21/55 ,  G06F9/38 ,  G06F21/75

Abstract: A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.

公开(公告)号：US11899607B2

公开(公告)日：2024-02-13

申请号：US17335378

申请日：2021-06-01

Applicant: Arm Limited

Inventor： Timothy Hayes ,  Alejandro Rico Carro ,  Tushar P. Ringe ,  Kishore Kumar Jagadeesha

IPC: G06F13/40 ,  G06F12/0875

CPC classification number: G06F13/4031 ,  G06F12/0875 ,  G06F2212/1024

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

公开(公告)号：US11797415B2

公开(公告)日：2023-10-24

申请号：US17271399

申请日：2019-08-30

Applicant: Arm Limited

Inventor： Timothy Hayes ,  Giacomo Gabrielli ,  Matthew James Horsnell

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3452 ,  G06F11/3024 ,  G06F11/3466

Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals. Further, history analysis circuitry is responsive to an analysis trigger to analyse the event history information in order to detect a reporting condition when the event history information indicates that a ratio between occurrences of the first event and the occurrences of the second event is outside an acceptable range. The history analysis circuitry is then responsive to detection of the reporting condition to assert a report signal. This provides a particularly efficient and effective mechanism for monitoring ratios of events within a data processing system.

公开(公告)号：US11042375B2

公开(公告)日：2021-06-22

申请号：US15665781

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jesse Garrett Beu ,  Alejandro Martinez Vicente ,  Timothy Hayes

IPC: G06F9/30

Abstract: An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations, are also provided.