公开(公告)号：US11531620B2

公开(公告)日：2022-12-20

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F12/0831 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US11146495B2

公开(公告)日：2021-10-12

申请号：US16550018

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Kishore Kumar Jagadeesha

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/835 ,  H04L12/46

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

公开(公告)号：US11181957B1

公开(公告)日：2021-11-23

申请号：US17102963

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Ramamoorthy Guru Prasadh ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  David Joseph Hawkins ,  Saira Samar Malik

IPC: G06F1/24 ,  H03K19/20 ,  G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K5/00

Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.

公开(公告)号：US11074206B1

公开(公告)日：2021-07-27

申请号：US17036225

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  Ashok Kumar Tummala ,  Rishabh Jain ,  Devi Sravanthi Yalamarthy

IPC: G06F13/28 ,  G06F13/40 ,  G06F9/46

Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

公开(公告)号：US20200241589A1

公开(公告)日：2020-07-30

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US11899607B2

公开(公告)日：2024-02-13

申请号：US17335378

申请日：2021-06-01

Applicant: Arm Limited

Inventor： Timothy Hayes ,  Alejandro Rico Carro ,  Tushar P. Ringe ,  Kishore Kumar Jagadeesha

IPC: G06F13/40 ,  G06F12/0875

CPC classification number: G06F13/4031 ,  G06F12/0875 ,  G06F2212/1024

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

公开(公告)号：US20220308997A1

公开(公告)日：2022-09-29

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US20210058335A1

公开(公告)日：2021-02-25

申请号：US16550018

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Kishore Kumar Jagadeesha

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/46 ,  H04L12/835

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

公开(公告)号：US10802534B2

公开(公告)日：2020-10-13

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08 ,  H03L7/091 ,  H03L7/081 ,  G06F1/24

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US10585449B1

公开(公告)日：2020-03-10

申请号：US16248456

申请日：2019-01-15

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/099

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.