公开(公告)号：US12147265B2

公开(公告)日：2024-11-19

申请号：US18057710

申请日：2022-11-21

Applicant: ATI Technologies ULC

Inventor： Yanfeng Wang ,  Shaofeng An

IPC: G06F1/12 ,  G06F1/08

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

公开(公告)号：US20240095404A1

公开(公告)日：2024-03-21

申请号：US17945750

申请日：2022-09-15

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Shaofeng An ,  Shiqi Sun ,  Michael James Tresidder ,  YanFeng Wang ,  Peter Malcolm Barnes

IPC: G06F21/64 ,  G06F16/23

CPC classification number: G06F21/64 ,  G06F16/2365

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

公开(公告)号：US20250103090A1

公开(公告)日：2025-03-27

申请号：US18476082

申请日：2023-09-27

Applicant: ATI Technologies ULC

Inventor： Shaofeng An ,  YanFeng Wang

IPC: G06F1/08

Abstract: An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US20240168515A1

公开(公告)日：2024-05-23

申请号：US18057710

申请日：2022-11-21

Applicant: ATI Technologies ULC

Inventor： Yanfeng Wang ,  Shaofeng An

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.