公开(公告)号：US20240168515A1

公开(公告)日：2024-05-23

申请号：US18057710

申请日：2022-11-21

Applicant: ATI Technologies ULC

Inventor： Yanfeng Wang ,  Shaofeng An

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

公开(公告)号：US12147265B2

公开(公告)日：2024-11-19

申请号：US18057710

申请日：2022-11-21

Applicant: ATI Technologies ULC

Inventor： Yanfeng Wang ,  Shaofeng An

IPC: G06F1/12 ,  G06F1/08

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

公开(公告)号：US11693465B2

公开(公告)日：2023-07-04

申请号：US17150600

申请日：2021-01-15

Applicant: ADVANCED MICRO DEVICES INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

CPC classification number: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US20210132675A1

公开(公告)日：2021-05-06

申请号：US17150600

申请日：2021-01-15

Applicant: ADVANCED MICRO DEVICES INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US10895901B1

公开(公告)日：2021-01-19

申请号：US16586817

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US20200174962A1

公开(公告)日：2020-06-04

申请号：US16204751

申请日：2018-11-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael J. Tresidder ,  Yanfeng Wang ,  Shiqi Sun

IPC: G06F13/42 ,  G06F13/20

Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.

公开(公告)号：US11132327B2

公开(公告)日：2021-09-28

申请号：US16204751

申请日：2018-11-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael J. Tresidder ,  Yanfeng Wang ,  Shiqi Sun

IPC: G06F13/42 ,  G06F13/20

Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.

公开(公告)号：US10541841B1

公开(公告)日：2020-01-21

申请号：US16130791

申请日：2018-09-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Shiqi Sun ,  Michael J. Tresidder ,  Yanfeng Wang

IPC: H03H7/30 ,  H04L25/03 ,  H04L7/00 ,  H04L25/02

Abstract: Systems, apparatuses, and methods for performing transmit equalization at a target high speed are disclosed. A computing system includes at least a transmitter, receiver, and a communication channel connecting the transmitter and the receiver. The communication channel includes a plurality of lanes which are subdivided into a first subset of lanes and a second subset of lanes. During equalization training, the first subset of lanes operate at a first speed while the second subset of lanes operate at a second speed. The first speed is the desired target speed for operating the communication link while the second speed is a relatively low speed capable of reliably carrying data over a given lane prior to equalization training. The first subset of lanes are trained at the first speed while feedback is conveyed from the receiver to the transmitter using the second subset of lanes operating at the second speed.