公开(公告)号：US20210391426A1

公开(公告)日：2021-12-16

申请号：US16898589

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： HIDEKI TAKEUCHI ,  Yung-Hsuan Yang

IPC分类号： H01L29/15 ,  H01L29/267 ,  H01L29/423 ,  H01L29/10

摘要： A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

公开(公告)号：US20200343367A1

公开(公告)日：2020-10-29

申请号：US16853884

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L29/78

摘要： A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

公开(公告)号：US20210391446A1

公开(公告)日：2021-12-16

申请号：US16898564

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： Hideki Takeuchi ,  Yung-Hsuan Yang

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L21/265

摘要： A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125°, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.

公开(公告)号：US11094818B2

公开(公告)日：2021-08-17

申请号：US16853884

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/66

摘要： A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

公开(公告)号：US11569368B2

公开(公告)日：2023-01-31

申请号：US16898564

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： Hideki Takeuchi ,  Yung-Hsuan Yang

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/10 ,  H01L21/02

摘要： A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125°, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.

公开(公告)号：US11469302B2

公开(公告)日：2022-10-11

申请号：US16898589

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： Hideki Takeuchi ,  Yung-Hsuan Yang

IPC分类号： H01L29/15 ,  H01L29/10 ,  H01L29/423 ,  H01L29/267

摘要： A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

公开(公告)号：US20200343380A1

公开(公告)日：2020-10-29

申请号：US16853875

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/78 ,  H01L29/15 ,  H01L29/06 ,  H01L29/10

摘要： A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

公开(公告)号：US11869968B2

公开(公告)日：2024-01-09

申请号：US17719242

申请日：2022-04-12

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/152 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

公开(公告)号：US11329154B2

公开(公告)日：2022-05-10

申请号：US16853875

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/66

摘要： A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

公开(公告)号：US11075078B1

公开(公告)日：2021-07-27

申请号：US16810957

申请日：2020-03-06

申请人： Atomera Incorporated

发明人： Nyles Wynn Cody ,  Keith Doran Weeks ,  Robert John Stephenson ,  Richard Burton ,  Yi-Ann Chen ,  Dmitri Choutov ,  Hideki Takeuchi ,  Yung-Hsuan Yang

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L29/15 ,  H01L29/10

摘要： A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.