公开(公告)号：US10373579B2

公开(公告)日：2019-08-06

申请号：US15614791

申请日：2017-06-06

申请人： AU OPTRONICS CORP.

发明人： Chun-Fan Chung ,  Tien-Lun Ting ,  Chia-Chi Tsai ,  Ming-Hung Tu ,  Chien-Huang Liao ,  Yu-Chieh Chen ,  Pin-Miao Liu

IPC分类号： G09G3/36 ,  G09G5/00

摘要： In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

公开(公告)号：US09697793B2

公开(公告)日：2017-07-04

申请号：US14590414

申请日：2015-01-06

申请人： AU OPTRONICS CORP.

发明人： Chun-Fan Chung ,  Tien-Lun Ting ,  Chia-Chi Tsai ,  Ming-Hung Tu ,  Chien-Huang Liao ,  Yu-Chieh Chen ,  Pin-Miao Liu

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/36

CPC分类号： G09G5/00 ,  G09G3/3674 ,  G09G2300/0413 ,  G09G2310/0267 ,  G09G2310/066 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0223

摘要： In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.