公开(公告)号：US20220368319A1

公开(公告)日：2022-11-17

申请号：US17517093

申请日：2021-11-02

申请人： AU Optronics Corporation

发明人： Yi-Chen LU ,  Hsu-Chi LI ,  Yi-Jan CHEN ,  Boy-Yiing JAW ,  Chin-Tang CHUANG ,  Chung-Hung CHEN

IPC分类号： H03K3/356 ,  H03K19/0185 ,  H03K17/10

摘要： A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

公开(公告)号：US20230238946A1

公开(公告)日：2023-07-27

申请号：US18187262

申请日：2023-03-21

申请人： AU Optronics Corporation

发明人： Yi-Chen LU ,  Hsu-Chi LI ,  Yi-Jan CHEN ,  Boy-Yiing JAW ,  Chin-Tang CHUANG ,  Chung-Hung CHEN

IPC分类号： H03K3/356 ,  H03K17/10 ,  H03K19/0185

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K19/018521

摘要： A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

公开(公告)号：US20220368320A1

公开(公告)日：2022-11-17

申请号：US17516730

申请日：2021-11-02

申请人： AU Optronics Corporation

发明人： Yi-Chen LU ,  Hsu-Chi LI ,  Yi-Jan CHEN ,  Boy-Yiing JAW ,  Chin-Tang CHUANG ,  Chung-Hung CHEN

IPC分类号： H03K5/02 ,  H03K19/0175

摘要： The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.