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公开(公告)号：US20240063832A1
公开(公告)日：2024-02-22
申请号：US17888664
申请日：2022-08-16
CPC分类号： H04B1/006 , H04B1/0028 , H04B1/04
摘要： Described herein are related to a device for communication. In one aspect, the device includes a first circuit configured to generate a first signal and a second signal at a first frequency, according to a third signal at a second frequency higher than the first frequency. The first signal and the second signal may have opposite phases with each other. In one aspect, the device includes a second circuit configured to provide a difference between the first signal and the second signal as a fourth signal. In one aspect, the device includes a third circuit configured to provide the first signal to the second circuit, and resonate at a third frequency between the first frequency and the second frequency. In one aspect, the device includes a fourth circuit configured to provide the second signal to the second circuit, and resonate at the third frequency.
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公开(公告)号：US20240063808A1
公开(公告)日：2024-02-22
申请号：US17892001
申请日：2022-08-19
IPC分类号： H03M1/10
CPC分类号： H03M1/1023
摘要： Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.
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公开(公告)号：US20240063809A1
公开(公告)日：2024-02-22
申请号：US17891871
申请日：2022-08-19
IPC分类号： H03M1/10
CPC分类号： H03M1/1042
摘要： A digital-to-analog converter (DAC) calibration system comprising: a DAC configured to convert digital input to an analog input, a detector configured to measure the analog outputs of the plurality of DAC unit cells and combine the analog outputs to create an overall analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.
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公开(公告)号：US12113542B2
公开(公告)日：2024-10-08
申请号：US17892001
申请日：2022-08-19
IPC分类号： H03M1/10
CPC分类号： H03M1/1023
摘要： Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.
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公开(公告)号：US20230353184A1
公开(公告)日：2023-11-02
申请号：US18304998
申请日：2023-04-21
IPC分类号： H04B1/40
CPC分类号： H04B1/40
摘要： In some aspects, the disclosure is directed to methods and systems for one or more line-drivers configured to selectively operate between a plurality of modes. When operating as a voltage-mode line-driver increased power efficiency may be realized. When operating as a current-mode line-driver, an increased transmission power may be realized. When operating in a dual/additive mode, still further increased transmission power may be realized.
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公开(公告)号：US20240106446A1
公开(公告)日：2024-03-28
申请号：US17950567
申请日：2022-09-22
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.
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公开(公告)号：US20240063807A1
公开(公告)日：2024-02-22
申请号：US18479019
申请日：2023-09-30
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.
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公开(公告)号：US20240063805A1
公开(公告)日：2024-02-22
申请号：US17889877
申请日：2022-08-17
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： Described herein are related to a device including a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal. In one aspect, the device includes a first circuit configured to generate a first signal. In one aspect, the device includes a second circuit coupled to the first circuit. The second circuit may be configured to generate a second signal, based on the first signal. The second signal may have a first edge according to the first signal. In one aspect, the device includes a third circuit coupled to the second circuit. The third circuit may be configured to generate a third signal having a second edge, in response to the first edge of the second signal. In one aspect, an amplitude of the third signal may correspond to one bit.
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公开(公告)号：US20240063776A1
公开(公告)日：2024-02-22
申请号：US17892003
申请日：2022-08-19
IPC分类号： H03H11/24
CPC分类号： H03H11/24
摘要： Described herein are related to a device for communication. In one aspect, the device a first circuit configured to generate a signal. In one aspect, the device includes a port. In one aspect, the device includes a set of switches. Each switch of the set of switches may be coupled in parallel between the first circuit and the port. In one aspect, the device includes a second circuit configured to enable a subset of the set of switches, according to an amplitude of the signal.
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