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1.发明公开公开(公告)号：US20240364355A1
公开(公告)日：2024-10-31
申请号：US18308796
申请日：2023-04-28
发明人： Pasindu Aluthwala , Andrew Adams
IPC分类号： H03M1/12
CPC分类号： H03M1/1245
摘要： A device may include one or more ring oscillators and circuitry. The one or more ring oscillators may include a plurality of rings. The circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. The circuitry may be configured to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals to one or more digital signals.
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公开(公告)号：US20240364334A1
公开(公告)日：2024-10-31
申请号：US18141344
申请日：2023-04-28
发明人： Hyung-Joon Jeon , Jun Cao , Seong Ho Lee , Anand J. Vasani
IPC分类号： H03K17/693
CPC分类号： H03K17/693
摘要： In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.
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公开(公告)号：US20240364266A1
公开(公告)日：2024-10-31
申请号：US18309007
申请日：2023-04-28
发明人： Zeng Zeng , Jan Mulder , Jan Roelof Westra
CPC分类号： H03F1/02 , H03F3/45475 , H03F2200/129 , H03F2203/45528
摘要： A system may include circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver and couple a first end of a second resistor to a second input terminal of the line driver. The circuitry may be configured to receive, at a second end of the first resistor, a first signal. The circuitry may be configured to receive, at a second end of the second resistor, a second signal. The circuitry may be configured to set at least one of the first resistor or the second resistor to cause the line driver to output a predetermined range of output voltages, based at least on a voltage sensed from at least one of the first signal or the second signal.
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公开(公告)号：US20240363503A1
公开(公告)日：2024-10-31
申请号：US18309308
申请日：2023-04-28
发明人： Dingyou Zhang , Li Sun
IPC分类号： H01L23/495 , H01L23/00 , H01L23/498
CPC分类号： H01L23/49575 , H01L23/4952 , H01L23/49827 , H01L24/09 , H01L24/49 , H01L2224/0903 , H01L2224/09102 , H01L2224/4903 , H01L2224/49107 , H01L2224/49421
摘要： The present invention relates to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device comprising a double-sided fanout die package is provided. On one surface of a main circuit board for the semiconductor device, regular single-sided flip-chip dies and tall SMT components are coupled, along with one or more double-sided fanout dies, which are stacked with corresponding sub-sized circuit boards that are also coupled to the same surface, with a smaller height than the tallest surface mount device. A portion of the metal routing and grounding connections in the main circuit board for one or more double-sided fanout dies can be transferred to the sub-sized circuit boards, thereby reducing the area of the main circuit board without increasing the number of circuit board layers. There are other embodiments as well.
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5.发明公开公开(公告)号：US20240340213A1
公开(公告)日：2024-10-10
申请号：US18132908
申请日：2023-04-10
发明人： Mohyee MIKHEMAR , Alvin Lai LIN , Andrew J. BLANKSBY , Sudharshan SRINIVASAN , Ahmed SAYED , Wei-Hong CHEN , Arya BEHZAD
IPC分类号： H04L27/36
CPC分类号： H04L27/364
摘要： A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.
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公开(公告)号：US12113542B2
公开(公告)日：2024-10-08
申请号：US17892001
申请日：2022-08-19
IPC分类号： H03M1/10
CPC分类号： H03M1/1023
摘要： Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.
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7.发明授权公开(公告)号：US12113065B2
公开(公告)日：2024-10-08
申请号：US17481204
申请日：2021-09-21
发明人： Qing Liu
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/66
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823431 , H01L29/0847 , H01L29/66795 , H01L29/7851
摘要： A fin-based field effect transistor (finFET) device may include a fin structure having a first portion, a second portion and a third portion. The finFET device may include a first gate structure disposed over at least part of the first portion, a first source/drain region disposed in the first portion, and a second drain/source region disposed in the third portion. Each of the first, second and third portions may include one or more fin portions. The total fin count in the second portion is fewer than the total fin count in the first portion. The second portion may include a drift region. Methods of fabricating a finFET are also disclosed. The finFET device provides a lower on-resistance and a higher breakdown voltage than conventional finFETs.
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公开(公告)号：US20240334567A1
公开(公告)日：2024-10-03
申请号：US18126927
申请日：2023-03-27
IPC分类号： H05B45/36 , H05B45/345
CPC分类号： H05B45/36 , H05B45/345
摘要： A device includes a first circuit, a ground, a reference voltage source that provides a reference voltage, and a first transistor that includes a first drain, a first source, and a first gate. The first circuit is coupled between the first source and the ground. The device has a second transistor that includes a second source and a second gate. The second transistor is biased as a source follower with the second source of the second transistor being set at the reference voltage. The first gate of the first transistor is coupled to the second gate of the second transistor, the first source has equal voltage as the second source, and the first circuit is coupled between the first source having the reference voltage and the ground to draw a constant current from the first source and to bias the first transistor in the saturation region to reduce parasitic capacitance.
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公开(公告)号：US20240333300A1
公开(公告)日：2024-10-03
申请号：US18126924
申请日：2023-03-27
CPC分类号： H03M1/462 , H03M1/0607
摘要： An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.
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公开(公告)号：US20240333296A1
公开(公告)日：2024-10-03
申请号：US18127508
申请日：2023-03-28
摘要： A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.
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