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公开(公告)号：US07155006B2
公开(公告)日：2006-12-26
申请号：US09960821
申请日：2001-09-21
CPC分类号： H04B3/03 , H04L25/063
摘要： A method and apparatus for outbound wave subtraction using a variable offset amplifier is described. The method includes calibration of a bi-directional signaling circuit in order to calculate one or more offset codes for cancellation of an outbound wave within a bi-directional communications link. Once the one or more offset codes are calculated, it is determined whether a dual inbound wave is received by the bi-directional signaling circuit. Once received, an offset code from the one or more calculated offset codes is selected according to a value of an outbound wave within the dual inbound/outbound wave. Finally, the outbound wave is cancelled from the dual inbound wave at an output of a variable offset amplifier using the selected offset code.
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2.发明授权Multiple input, fully differential, wide common-mode, folded-cascode amplifier 失效多输入，全差分，宽共模，折叠共源共栅放大器公开(公告)号：US06628168B2
公开(公告)日：2003-09-30
申请号：US09896193
申请日：2001-06-28
申请人： Aaron K. Martin , Stephen R. Mooney
发明人： Aaron K. Martin , Stephen R. Mooney
IPC分类号： H03F345
CPC分类号： H03F3/45219
摘要： A multiple input, fully differential amplifier. Embodiments make use of complementary differential transistors pairs connected with cascode transistors to form folded cascode pairs, to achieve wide common mode range, high common mode rejection, and high gain.
摘要翻译： 多输入，全差分放大器。 实施例利用与共源共栅晶体管连接的互补差分晶体管对形成折叠共源共栅对，实现宽共模范围，高共模抑制和高增益。
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3.发明授权公开(公告)号：US06597198B2
公开(公告)日：2003-07-22
申请号：US09972327
申请日：2001-10-05
IPC分类号： H03K190175
CPC分类号： H04L25/45 , H03K19/018592 , H04L7/0004
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous bidirectional port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output current and a variable output resistance. Prior to synchronization, the driver has a low output current and low output resistance. When the simultaneous bidirectional port is ready to communicate, the variable output resistance is increased. When both simultaneous bidirectional ports are ready, the variable output resistance is set to properly terminate the line, and the variable output current is set to provide a desired voltage swing.
摘要翻译： 耦合到总线的同时双向端口组合同步电路和数据收发器电路。 组合数据和同步收发器电路将端口与耦合到同一总线的另一个同时双向端口同步。 组合数据和同步收发器电路包括具有可变输出电流和可变输出电阻的驱动器。 在同步之前，驱动器具有低输出电流和低输出电阻。 当同时双向端口准备通信时，可变输出电阻增加。 当两个同时双向端口准备就绪时，可变输出电阻被设置为适当地终止线路，并且可变输出电流被设置为提供期望的电压摆幅。
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公开(公告)号：US06538502B2
公开(公告)日：2003-03-25
申请号：US09749061
申请日：2000-12-27
IPC分类号： H03F102
CPC分类号： H03F3/45977 , H03F3/45995 , H03F2203/45544
摘要： A differential amplifier has input and output terminals to generate a second signal at the output terminals for a first signal. The amplifier has feedback switches between the output terminals and the input terminals. Offset capacitors are coupled to the differential amplifier at the input terminals and reference voltages via charging switches to provide offsets for the first signal form the reference voltages via input switches.
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公开(公告)号：US06507225B2
公开(公告)日：2003-01-14
申请号：US09835600
申请日：2001-04-16
申请人： Aaron K. Martin , Stephen R. Mooney
发明人： Aaron K. Martin , Stephen R. Mooney
IPC分类号： H03K300
CPC分类号： H03K19/018564 , H03K19/01721 , H04L25/0266 , H04L25/03878
摘要： A simultaneous bidirectional data port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. The current mode return driver is scalable to reduce current requirements. Each driver is divided into driver segments. Some driver segments are driven by outbound data, and other driver segments are driven by pre-equalization data. Variable pre-equalization is provided by a pre-driver that selects the number of driver segments to be driven with pre-equalization data and the number of driver segments to be driven by outbound data.
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公开(公告)号：US20080181331A1
公开(公告)日：2008-07-31
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
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公开(公告)号：US07171510B2
公开(公告)日：2007-01-30
申请号：US09752880
申请日：2000-12-28
申请人： Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
CPC分类号： G06F11/221
摘要： The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.
摘要翻译： 本发明在一个实施例中提供了一种用于非干涉地观察，回送和读取由总线和无线通信之一发送的信号而不干扰总线的电气特性而不增加总线等待时间并且不增加信号不连续性的装置，方法和装置 。 在一方面，具有触发器的缓冲器与连接到存储器总线的部件耦合，缓冲器将信号回送到可观测端口，并且诊断装置读取回送信号。 一方面，总线是具有三元逻辑电平的同时双向（SBD）总线之一，单端总线，差分总线，光耦合总线，芯片组总线，前端总线，输入/输出（ I / O）总线，外设组件接口（PCI）总线和工业标准架构（ISA）总线。 在一个方面，缓冲器回波频率在500MHz之间的总线信号。 和5 GHz。 在一方面，缓冲器响应具有至少5GHz频率的总线信号。
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公开(公告)号：US06538584B2
公开(公告)日：2003-03-25
申请号：US09752883
申请日：2000-12-28
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03M700
CPC分类号： G11C7/10
摘要： In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.
摘要翻译： 在一些实施例中，本发明涉及包括第一组导体的电路，以承载当前位组和最后位组电路以保持并提供最后位组。 电路还包括耦合到互连导体的驱动器以提供从驱动器到互连导体的信号，以及用于接收最后位组和当前位组的编码器，并确定是提供当前位组还是当前位的编码版本 设置为司机。
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9.发明授权公开(公告)号：US06529037B1
公开(公告)日：2003-03-04
申请号：US09951909
申请日：2001-09-13
IPC分类号： H03K19003
CPC分类号： H04L25/0276 , H04L25/028 , H04L25/0292
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous data port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output impedance. Prior to synchronization, the driver has an imbalanced output impedance, and after synchronization, the driver has a substantially balanced output impedance.
摘要翻译： 耦合到总线的同时双向端口组合同步电路和数据收发器电路。 组合数据和同步收发器电路将端口与耦合到同一总线的另一个同时的数据端口同步。 组合数据和同步收发器电路包括具有可变输出阻抗的驱动器。 在同步之前，驱动器具有不平衡的输出阻抗，并且在同步之后，驱动器具有基本平衡的输出阻抗。
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公开(公告)号：US06522174B2
公开(公告)日：2003-02-18
申请号：US09835892
申请日：2001-04-16
申请人： Aaron K. Martin , Stephen R. Mooney
发明人： Aaron K. Martin , Stephen R. Mooney
IPC分类号： H03K19094
CPC分类号： H04L25/0282 , H03K19/01721 , H03K19/018528 , H04L25/0272 , H04L25/0294
摘要： A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.
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