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    Simultaneous transmission and reception of signals in different frequency bands over a bus line
    1.
    发明授权
    Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
    在总线上同时发送和接收不同频段的信号

    公开(公告)号：US07177288B2

    公开(公告)日：2007-02-13

    申请号：US09998008

    申请日：2001-11-28

    申请人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    发明人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    IPC分类号： H04L5/14

    CPC分类号： H04L5/1423

    摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

    摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。

    Using a timing strobe for synchronization and validation in a digital logic device
    2.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
    3.
    发明授权
    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
    具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化

    公开(公告)号：US06373289B1

    公开(公告)日：2002-04-16

    申请号：US09752895

    申请日：2000-12-26

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： H03K1900

    CPC分类号： H03L7/0812 ,  H03K5/135 ,  H04L25/242

    摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

    摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。

    Integrated circuit stubs in a point-to-point system
    4.
    发明授权
    Integrated circuit stubs in a point-to-point system 有权
    集成电路存根在点对点系统中

    公开(公告)号：US06747474B2

    公开(公告)日：2004-06-08

    申请号：US09797480

    申请日：2001-02-28

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K1716

    CPC分类号： H04L5/14 ,  H03K19/01759 ,  H04L25/0278 ,  H04L25/24

    摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

    摘要翻译： 在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。 所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体 电路芯片。 集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号 并将它们驱动到第三导体上。

    Memory pass-band signaling
    10.
    发明授权
    Memory pass-band signaling 有权
    存储器通带信令

    公开(公告)号：US06845424B2

    公开(公告)日：2005-01-18

    申请号：US10062034

    申请日：2002-01-31

    申请人： Bryan K. Casper ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  James E. Jaussi

    发明人： Bryan K. Casper ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  James E. Jaussi

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/06

    摘要： A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

    摘要翻译： 存储器系统提供包括分配有频率通带的多个存储器件或存储器器件组。 每个存储器件包括频率转换电路，用于将数据信号上变频和下转换到分配的频率通带。 一些实施例包括通过将多个频率通带分配给每个存储器件或存储器组来同时在存储器件与控制器之间进行双向通信。 存储器系统基板在存储器件占用面积和其它器件占用面积之间提供带通滤波器。