公开(公告)号：US20060165121A1

公开(公告)日：2006-07-27

申请号：US11044479

申请日：2005-01-27

申请人： Aaron MacDonald ,  Tim White ,  Chris Anastasiadis

发明人： Aaron MacDonald ,  Tim White ,  Chris Anastasiadis

IPC分类号： H04J3/16 ,  H04J3/22

CPC分类号： H04L41/0806 ,  H04L12/46 ,  H04L69/08

摘要： Communication protocol interface systems and methods are disclosed. A predetermined type of content of communication traffic of a first communication protocol, illustratively control information, is translated into a corresponding type of content of communication traffic of a second communication protocol. The translated communication traffic is transferred to a first component of a communication device, which is configured to transfer the corresponding type of content to a second component of the communication device. The second component is configured for processing the predetermined type of content. In some embodiments, other types of content are translated for direct processing by the first component. Mechanisms are thereby provided, for example, for transferring control information through a packet processor to a host processor, while allowing data to be processed normally by the packet processor.

摘要翻译： 公开了通信协议接口系统和方法。 第一通信协议的通信流量的预定类型的内容，示例性地控制信息被转换成第二通信协议的通信业务的相应类型的内容。 被翻译的通信业务被传送到通信设备的第一组件，其被配置为将相应类型的内容传送到通信设备的第二组件。 第二组件配置用于处理预定类型的内容。 在一些实施例中，翻译其他类型的内容以供第一组件直接处理。 从而提供了例如用于通过分组处理器将控制信息传送到主机处理器的机制，同时允许分组处理器正常处理数据。

公开(公告)号：US20070071029A1

公开(公告)日：2007-03-29

申请号：US11234167

申请日：2005-09-26

申请人： Tim White ,  Aaron MacDonald ,  Dion Pike

发明人： Tim White ,  Aaron MacDonald ,  Dion Pike

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L12/4633 ,  H04L45/04 ,  H04L45/50

摘要： A system and method are provided for implementing CESOP inexpensively yet effectively implemented across an MPLS or an IP network. A Zarlink chip provides CESOP functionality, providing a TDM pseudowire by converting TDM streams into Ethernet packets. These Ethernet packets can be processed by a Marvell chip, which has the ability to perform QoS functions on the packets. The Marvell chip converts the Ethernet packets into MPLS or IP packets for transmission over a packet network. Use of a single virtual circuit label, invisible to the packet network for routing purposes, within the Ethernet packet allows Marvell chips at each end of the emulated circuit to tie traffic to a particular customer and to thereby apply appropriate QoS constraints.

摘要翻译： 提供了一种用于在MPLS或IP网络上廉价实施CESOP而有效实现的系统和方法。 Zarlink芯片提供CESOP功能，通过将TDM流转换为以太网数据包提供TDM伪线。 这些以太网数据包可以由Marvell芯片处理，该芯片具有对数据包执行QoS功能的能力。 Marvell芯片将以太网数据包转换为MPLS或IP数据包，以通过数据包网络进行传输。 在以太网数据包内使用单个虚拟电路标签，对分组网络不可见，用于路由目的，允许仿真电路每端的Marvell芯片将流量与特定客户绑定，从而应用适当的QoS约束。

公开(公告)号：US20070217336A1

公开(公告)日：2007-09-20

申请号：US11377578

申请日：2006-03-17

申请人： Jason Sterne ,  Robert Johnson ,  Aaron MacDonald ,  Richard Grieve ,  James Schriel

发明人： Jason Sterne ,  Robert Johnson ,  Aaron MacDonald ,  Richard Grieve ,  James Schriel

IPC分类号： H04J1/16 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L47/266 ,  H04L47/30 ,  H04L47/32 ,  H04L49/90 ,  Y02D50/10

摘要： A method for incorporating a queuing device as a lossless processing stage in a network device in a communications network, comprising: monitoring a depth of a queue in the queuing device, the queue for receiving packets from an upstream device within the network device, the queuing device acting as a discard point by discarding packets when the queue is full; and, if the depth passes a predetermined threshold, sending a message to the upstream device to reduce a rate at which packets are sent to the queuing device to prevent the queue from filling and thereby preventing packet discarding and loss by the queuing device.

摘要翻译： 一种在通信网络中的网络设备中将排队设备作为无损处理级并入的方法，包括：监视队列设备中的队列的深度，用于从网络设备内的上游设备接收分组的队列，排队 设备在队列满时通过丢弃报文作为丢弃点; 并且如果深度通过预定阈值，则向上游设备发送消息以降低分组被发送到排队设备的速率，以防止队列填满，从而防止排队设备丢包和丢失。

公开(公告)号：US20070208926A1

公开(公告)日：2007-09-06

申请号：US11366661

申请日：2006-03-03

申请人： Richard Grieve ,  Aaron MacDonald ,  James Schriel

发明人： Richard Grieve ,  Aaron MacDonald ,  James Schriel

IPC分类号： G06F15/177

CPC分类号： G06F9/4401

摘要： A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

摘要翻译： 提供了一种用于将微处理器的引导配置PROM存储在FPGA中的方法和装置。 微处理器的引导接口（如I2C接口）通向FPGA而不是PROM。 引导配置作为图像存储在FPGA中，微处理器使用其正常引导接口访问引导配置。 以这种方式，不需要专用的引导PROM，从而在微处理器所在的卡上节省不动产。 引导配置也比如果引导配置存储在专用PROM上更容易修改，例如用于版本升级或诊断。 不同的引导配置可以作为软件映像存储在单独的管家处理器上，用于加载到FPGA中。

公开(公告)号：US20050097556A1

公开(公告)日：2005-05-05

申请号：US10695953

申请日：2003-10-30

申请人： Sean Code ,  Aaron MacDonald

发明人： Sean Code ,  Aaron MacDonald

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4881

摘要： A method and apparatus are provided for scheduling tasks within a computing device such as a communication switch. When a task is to be scheduled, other tasks in the work queue are analyzed to see if any can be executed simultaneously with the task to be scheduled. If so, the two tasks are combined to form a combined task, and the combined task is placed within the job queue. In addition, if the computing device has insufficient resources to execute the task to be scheduled, the task is placed back into the work queue for future scheduling. This is done in a way which avoids immediate reselection of the task for scheduling. Task processing efficiency is increased, since combining tasks reduces the waiting time for lower priority tasks, and tasks for which there are insufficient resources are delayed only a short while before a new scheduling attempt, rather than rejecting the task altogether.

摘要翻译： 提供了一种用于在诸如通信交换机的计算设备内调度任务的方法和装置。 当要安排任务时，分析工作队列中的其他任务，以查看是否可以与要调度的任务同时执行任务。 如果是这样，则将两个任务组合以形成组合任务，并且组合的任务被放置在作业队列内。 此外，如果计算设备没有足够的资源来执行要调度的任务，则将任务放回到工作队列中以供将来调度。 这样做是为了避免立即重新选择任务进行调度。 任务处理效率提高，因为组合任务减少了较低优先级任务的等待时间，而资源不足的任务在新的调度尝试之前只会延迟一段时间，而不是完全拒绝任务。