-
公开(公告)号:US20200006572A1
公开(公告)日:2020-01-02
申请号:US16022494
申请日:2018-06-28
申请人: Abhishek A. SHARMA , Yih WANG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Nazila HARATIPOUR , Benjamin CHU-KUNG , Seung Hoon SUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Matthew V. METZ
发明人: Abhishek A. SHARMA , Yih WANG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Nazila HARATIPOUR , Benjamin CHU-KUNG , Seung Hoon SUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Matthew V. METZ
IPC分类号: H01L29/786 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/66
摘要: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
-
公开(公告)号:US20200006575A1
公开(公告)日:2020-01-02
申请号:US16024682
申请日:2018-06-29
申请人: Gilbert DEWEY , Aaron LILAK , Van H. LE , Abhishek A. SHARMA , Tahir GHANI , Willy RACHMADY , Rishabh MEHANDRU , Nazila HARATIPOUR , Jack T. KAVALIEROS , Benjamin CHU-KUNG , Seung Hoon SUNG , Shriram SHIVARAMAN
发明人: Gilbert DEWEY , Aaron LILAK , Van H. LE , Abhishek A. SHARMA , Tahir GHANI , Willy RACHMADY , Rishabh MEHANDRU , Nazila HARATIPOUR , Jack T. KAVALIEROS , Benjamin CHU-KUNG , Seung Hoon SUNG , Shriram SHIVARAMAN
IPC分类号: H01L29/786 , H01L29/66
摘要: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.
-
公开(公告)号:US20190304982A1
公开(公告)日:2019-10-03
申请号:US15943576
申请日:2018-04-02
申请人: Abhishek A. SHARMA , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Yih WANG , Benjamin CHU-KUNG , Shriram SHIVARAMAN
发明人: Abhishek A. SHARMA , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Yih WANG , Benjamin CHU-KUNG , Shriram SHIVARAMAN
IPC分类号: H01L27/108
摘要: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.
-
-