MOBILE DEVICE APPLICATIONS FOR COMPUTER-TELEPHONY SYSTEMS
    2.
    发明申请
    MOBILE DEVICE APPLICATIONS FOR COMPUTER-TELEPHONY SYSTEMS 有权
    用于计算机电话系统的移动设备应用

    公开(公告)号:US20130244632A1

    公开(公告)日:2013-09-19

    申请号:US13424093

    申请日:2012-03-19

    IPC分类号: H04W4/00 H04M3/42

    摘要: On a mobile telecommunications device, computer-executable code executes to facilitate interactions between the user of the mobile telecommunications device and a call center or other computer-telephony integration equipment. The computer-executable code includes instructions that request at least one operation to be performed at a call center, where the call center includes a call center controller, an interactive voice response system component, and at least one agent. At least in part, a wireless network transmits the request from the mobile telecommunications device to the call center controller.

    摘要翻译: 在移动电信设备上,执行计算机可执行代码以促进移动电信设备的用户与呼叫中心或其他计算机电话集成设备之间的交互。 计算机可执行代码包括请求在呼叫中心执行的至少一个操作的指令,其中呼叫中心包括呼叫中心控制器,交互式语音响应系统组件和至少一个代理。 至少部分地,无线网络将来自移动电信设备的请求发送到呼叫中心控制器。

    Fishing Lure with Spinning Device

    公开(公告)号:US20210000094A1

    公开(公告)日:2021-01-07

    申请号:US16920486

    申请日:2020-07-03

    申请人: Michael Dunbar

    发明人: Michael Dunbar

    IPC分类号: A01K85/10

    摘要: An improved fishing lure with a spinning device is shown and described. The fishing lure with a spinning device includes a hook located at one end of the fishing lure. A shaft is attached to the hook having a spinning device located thereon. At least one spacer device is located on the shaft between the end of the hook and the spinning device. An eyelet is located at an end of the shaft opposite the hook.

    Layered capacitor architecture and fabrication method
    4.
    发明授权
    Layered capacitor architecture and fabrication method 有权
    分层电容器结构和制造方法

    公开(公告)号:US07511939B2

    公开(公告)日:2009-03-31

    申请号:US11895339

    申请日:2007-08-24

    IPC分类号: H01G4/228

    摘要: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

    摘要翻译: 分层电容器结构包括形成在提供机械支撑的绝缘表面上方的两个或更多个半导体/电介质板,其中所述板以垂直堆叠布置在绝缘表面上。 绝缘层在每个板上,被图案化和蚀刻以提供允许一个板的顶部与随后的板的底部物理和电接触的开口。 通过绝缘层提供接触开口,每个绝缘层提供对相应半导体层的访问,并且与任何其它半导体/电介质板绝缘。 通过接触开口的电触点提供到相应半导体层的电连接。 本结构可以包括根据需要提供期望的总电容或电容范围的堆叠层数。

    Semiconductor device interconnection contact and fabrication method
    5.
    发明申请
    Semiconductor device interconnection contact and fabrication method 有权
    半导体器件互连接触和制造方法

    公开(公告)号:US20070059921A1

    公开(公告)日:2007-03-15

    申请号:US11223367

    申请日:2005-09-09

    IPC分类号: H01L21/4763 H01L21/44

    CPC分类号: H01L21/76838

    摘要: A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and etch steps are then performed to remove interconnection trace metallization that is in close proximity to the active device regions, while leaving the traces' diffusion barrier layer intact to provide conductive paths to the devices, thereby reducing metallization-induced mechanical stress which might otherwise cause device instability.

    摘要翻译: 半导体器件互连接触和制造方法包括在半导体衬底上制造一个或多个有源器件。 扩散阻挡层沉积在器件上,随后沉积Al基金属化层。 扩散阻挡层和金属化层被掩蔽和蚀刻以限定互连迹线。 然后执行掩模和蚀刻步骤以去除紧邻有源器件区域的互连迹线金属化,同时留下迹线的扩散阻挡层完整以提供到器件的导电路径,从而减少金属化引起的机械应力,否则可能会导致 导致设备不稳定。

    Layered capacitor architecture and fabrication method
    6.
    发明申请
    Layered capacitor architecture and fabrication method 有权
    分层电容器结构和制造方法

    公开(公告)号:US20080062613A1

    公开(公告)日:2008-03-13

    申请号:US11895339

    申请日:2007-08-24

    IPC分类号: H01G4/30 H01G9/00

    摘要: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

    摘要翻译: 分层电容器结构包括形成在提供机械支撑的绝缘表面上方的两个或更多个半导体/电介质板,其中所述板以垂直堆叠布置在绝缘表面上。 绝缘层在每个板上,被图案化和蚀刻以提供允许一个板的顶部与随后的板的底部物理和电接触的开口。 通过绝缘层提供接触开口,每个绝缘层提供对相应半导体层的访问,并且与任何其它半导体/电介质板绝缘。 通过接触开口的电触点提供到相应半导体层的电连接。 本结构可以包括根据需要提供期望的总电容或电容范围的堆叠层数。

    Semiconductor device interconnection contact and fabrication method
    7.
    发明授权
    Semiconductor device interconnection contact and fabrication method 有权
    半导体器件互连接触和制造方法

    公开(公告)号:US07776739B2

    公开(公告)日:2010-08-17

    申请号:US11223367

    申请日:2005-09-09

    CPC分类号: H01L21/76838

    摘要: A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and etch steps are then performed to remove interconnection trace metallization that is in close proximity to the active device regions, while leaving the traces' diffusion barrier layer intact to provide conductive paths to the devices, thereby reducing metallization-induced mechanical stress which might otherwise cause device instability.

    摘要翻译: 半导体器件互连接触和制造方法包括在半导体衬底上制造一个或多个有源器件。 扩散阻挡层沉积在器件上,随后沉积Al基金属化层。 扩散阻挡层和金属化层被掩蔽和蚀刻以限定互连迹线。 然后执行掩模和蚀刻步骤以去除紧邻有源器件区域的互连迹线金属化,同时留下迹线的扩散阻挡层完整以提供到器件的导电路径,从而减少金属化引起的机械应力,否则可能会导致 导致设备不稳定。