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公开(公告)号：US6049362A
公开(公告)日：2000-04-11
申请号：US601486
申请日：1996-02-14
CPC分类号： H04N19/86 , H04N19/105 , H04N19/112 , H04N19/137 , H04N19/139 , H04N19/149 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/503 , H04N19/51 , H04N19/527 , H04N19/61 , H04N19/146 , H04N19/152
摘要： A method of and apparatus for identifying a Dual Prime motion estimation best match and generating motion vectors pertaining thereto for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The Dual Prime method of motion estimation described herein includes a method of generating motion vectors. The motion vectors point from a macroblock in a current field to a macroblock in a past field for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The first step in the method is defining a macroblock in a parity field of the current picture. Next, the preceding field of the same or opposite parity is searched to find a first best match macroblock in the preceding field. Once a best match macroblock is found, a vector is formed from the current macroblock in the current parity field to the first best match macroblock in the preceding parity field. This vector is scaled so that it refers to a second dual prime macroblock in the opposite parity field, that is the parity field of opposite parity with respect to the first best match macroblock which defines the center of a dual prime search window. Then, the average of the first best match macroblock and the set of second dual prime macroblocks in the dual prime search window is taken and the search window is searched to determine the best match dual prime macroblock. The search is typically conducted at half pixel locations inside a one square pixel dual prime search window. The appropriate dual prime motion vector and differential motion vector (dmv) are formed. These are motion vectors which point to both the first best match macroblock and the best match dual prime macroblock.
摘要翻译： 用于识别双重素质运动估计的方法和装置在具有F1和F2奇偶校验的图像的运动图像中最佳地匹配并产生与其相关的用于画面间视频压缩的运动矢量。 本文描述的双重运动估计方法包括产生运动矢量的方法。 在具有F1和F2奇偶校验图像的运动图像中，运动矢量从当前场中的宏块指向用于画面间视频压缩的过去场中的宏块。 该方法的第一步是定义当前图像的奇偶校验字段中的宏块。 接下来，搜索相同或相反奇偶校验的前一个字段以找到前一字段中的第一最佳匹配宏块。 一旦找到了最佳匹配宏块，则从当前奇偶校验字段中的当前宏块到先前奇偶校验字段中的第一最佳匹配宏块形成向量。 该向量被缩放，使得它指向相对奇偶校验字段中的第二双优先宏块，即相对于定义双重搜索窗口的中心的第一最佳匹配宏块的相对奇偶校验的奇偶校验字段。 然后，获取双重搜索窗口中的第一最佳匹配宏块和第二双优先宏块的平均值，并搜索搜索窗口以确定最佳匹配双优先宏块。 搜索通常在一个正方形像素双重搜索窗口内的半个像素位置进行。 形成适当的双质量运动矢量和微分运动矢量（dmv）。 这些是指向第一最佳匹配宏块和最佳匹配双优先宏块的运动矢量。
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公开(公告)号：US5870437A
公开(公告)日：1999-02-09
申请号：US740810
申请日：1996-11-01
摘要： A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously. The serial bit stream and digital strobe signal are asynchronous relative to the clock. Hardware logic determines when contents of the third register is same as contents of the second register; this indicates termination of the serial bit stream and digital strobe signal.
摘要翻译： 检测器检测串行比特流的结束，其中串行比特流基于一个时钟，并且检测器（和其他相关联的电路）基于不同的异步时钟。 异或逻辑块根据IEEE高性能串行总线规范1394接收串行比特流和数字选通信号。基于该标准，串行比特流和数字选通信号中的一个但不是两个在每个数据间隔改变水平。 当串行位流和数字选通信号存在时，异或逻辑块输出周期信号，而在串行位流终止时输出恒定的数字电平和数字选通信号。 检测器还包括耦合以接收接收器的输出的第一寄存器，耦合以接收第一寄存器的输出的第二寄存器和耦合以接收第二寄存器的输出的第三寄存器。 所有三个寄存器同时被同步。 串行比特流和数字选通信号相对于时钟是异步的。 硬件逻辑确定第三寄存器的内容何时与第二寄存器的内容相同; 这表示串行比特流和数字选通信号的终止。
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公开(公告)号：US5805088A
公开(公告)日：1998-09-08
申请号：US740811
申请日：1996-11-01
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers. A third clock triggers the fifth and sixth registers simultaneously to latch bits 0 and 2, respectively, of a series of four bits. A fourth clock triggers the seventh and eight registers simultaneously to latch bits 1 and 3, respectively, of the series of four bits.
摘要翻译： 设备将基于一个时钟的串行数据转换为基于不同异步时钟的并行数据。 数据转换器包括一个包括第一和第二寄存器的寄存器组和包括第三和第四寄存器的另一寄存器组。 第一寄存器的数据输入和第三寄存器的数据输入被耦合以接收串行数据。 第二寄存器的数据输入耦合到第一寄存器的数据输出。 第四寄存器的数据输入耦合到第三寄存器的数据输出。 第一时钟同时触发第一和第二寄存器，第二时钟同时触发第三和第四寄存器。 第一和第二时钟彼此交替。 第五，第六，第七和第八寄存器具有耦合到第一，第二，第三和第四寄存器的相应数据输出的各自的数据输入。 第三个时钟同时触发第五和第六寄存器，分别锁存一系列四位的位0和2。 第四个时钟同时触发第七个和第八个寄存器，分别锁存四个比特序列中的位1和3。
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4.发明授权Efficient, flexible motion estimation architecture for real time MPEG2 compliant encoding 失效高效，灵活的运动估计架构，用于实时MPEG2兼容编码公开(公告)号：US06549575B1
公开(公告)日：2003-04-15
申请号：US08745584
申请日：1996-11-07
申请人： Adrian Stephen Butter , John Mark Kaczmarczyk , Agnes Yee Ngai , Edward Francis Westermann , Robert J. Yagley
发明人： Adrian Stephen Butter , John Mark Kaczmarczyk , Agnes Yee Ngai , Edward Francis Westermann , Robert J. Yagley
IPC分类号： H04N732
CPC分类号： H04N19/53
摘要： Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.
摘要翻译： 对在参考图像中的像素的至少一个搜索单元中进行分层搜索的数字视频数据流的时间压缩，以找到当前宏块的最佳匹配。 随后在参考图片中构建当前宏块和最佳匹配宏块之间的运动矢量。
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公开(公告)号：US5768537A
公开(公告)日：1998-06-16
申请号：US605559
申请日：1996-02-22
CPC分类号： H04N19/423 , H04N19/42 , H04N19/61 , H04N11/044 , H04N11/20 , H04N5/147
摘要： A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.
摘要翻译： 一种可扩展架构MPEG2兼容数字视频编码器系统，其具有仅具有I帧视频编码器模块，具有离散余弦变换处理器，量化单元，可变长度编码器，FIFO缓冲器和压缩存储接口，用于生成I帧 包含比特流。 对于IPB比特流，该系统包括具有参考存储器接口，运动估计和补偿能力，反量化和反离散余弦变换的第二处理器元件和运动补偿装置; 以及至少一个第三处理器元件运动估计。 该系统可以是单个集成电路芯片或多个集成电路芯片的形式，其为每个处理器，I帧视频编码器模块，第二处理器元件和第三处理器元件之一。 可以有一个或多个第三处理器单元。
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