公开(公告)号：US20250006246A1

公开(公告)日：2025-01-02

申请号：US18344812

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Clinton Harold Parker

IPC: G11C11/408 ,  G11C11/4076 ,  H03K19/017

Abstract: An apparatus and method for both reducing power consumption and increasing read access stability of a memory array. An integrated circuit includes a memory array with memory bit cells arranged as multiple rows and multiple columns. The array also includes multiple word line driver circuits configured to generate a corresponding word line for multiple rows. The array includes an underdrive circuit configured to adjust, via a configurable resistor-capacitor circuit, a rate of change of a voltage level of a word line. The configurable resistor-capacitor circuit controls the store data rate of the charging of the selected word line and allows the selected word line to charge to the power supply voltage. The configurable resistor-capacitor circuit controls the rate of charging without creating a direct current path between the power supply voltage and the ground reference level that would increase power consumption.