公开(公告)号：US20180115306A1

公开(公告)日：2018-04-26

申请号：US15298871

申请日：2016-10-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepon Saha ,  Arun Sundaresan Iyer

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A native edge-triggered master-slave flip-flop exploits native latch topologies to create an edge-triggered master-slave flip-flop using a single clock phase having substantially reduced clock power consumption and substantially improved hold timing margin as compared to the clock power consumption and hold timing margin of a conventional master-slave flip-flop and other low power flip-flops.