公开(公告)号：US09372499B2

公开(公告)日：2016-06-21

申请号：US14159967

申请日：2014-01-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Arun Sundaresan Iyer ,  Alok Baluni ,  Aaron Grenat

IPC: H03B19/00 ,  G06F1/04 ,  H03K19/20 ,  H03K5/00 ,  H03K19/00

CPC classification number: G06F1/04 ,  G06F1/10 ,  H03K5/00006 ,  H03K19/0013 ,  H03K19/20

Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

Abstract translation: 时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有 分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地 向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一NAND门的输出而提供第一和第二控制信号 第一和第二NAND门。

公开(公告)号：US20180115306A1

公开(公告)日：2018-04-26

申请号：US15298871

申请日：2016-10-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepon Saha ,  Arun Sundaresan Iyer

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A native edge-triggered master-slave flip-flop exploits native latch topologies to create an edge-triggered master-slave flip-flop using a single clock phase having substantially reduced clock power consumption and substantially improved hold timing margin as compared to the clock power consumption and hold timing margin of a conventional master-slave flip-flop and other low power flip-flops.

公开(公告)号：US20230403415A1

公开(公告)日：2023-12-14

申请号：US17838552

申请日：2022-06-13

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Ihab Amer ,  Gabor Sines ,  Haibo Liu ,  Khaled Mammou ,  Arun Sundaresan Iyer

IPC: H04N21/2343 ,  H04N21/4402 ,  H04N21/442

CPC classification number: H04N21/2343 ,  H04N21/4402 ,  H04N21/44209

Abstract: Adaptive decoder-drive encoder reconfiguration techniques are described. In one example, techniques include detecting an operational condition at a consumer using a sensor, the consumer receiving a communication of digital content from an encoder; generating an adaptation instruction by the decoder based on the detecting; transmitting the adaptation instruction by the decoder for receipt by the encoder; and receiving an adapted communication of the digital content generated by the encoder, the adapted communication caused by reconfiguration of the encoder based on the adaptation instruction received from the decoder.

公开(公告)号：US10805643B2

公开(公告)日：2020-10-13

申请号：US15085562

申请日：2016-03-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Ihab Amer ,  Gabor Sines ,  Khaled Mammou ,  Haibo Liu ,  Arun Sundaresan Iyer

IPC: G06F1/32 ,  H04N19/895 ,  H04N19/66 ,  H04N19/70

Abstract: Various codecs and methods of using the same are disclosed. In one aspect, a method of processing video data is provided that includes encoding or decoding the video data with a codec in aggressive deployment and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re-decoding the video data in a non-aggressive deployment or generating a skip picture.

公开(公告)号：US09319037B2

公开(公告)日：2016-04-19

申请号：US14171469

申请日：2014-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

IPC: H03B19/00 ,  H03K5/13 ,  H03K5/00

CPC classification number: H03K5/131 ,  H03K2005/00058

Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

公开(公告)号：US20150222277A1

公开(公告)日：2015-08-06

申请号：US14171469

申请日：2014-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

IPC: H03L7/081 ,  H03K5/13

CPC classification number: H03K5/131 ,  H03K2005/00058

Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

公开(公告)号：US20150205323A1

公开(公告)日：2015-07-23

申请号：US14159967

申请日：2014-01-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Arun Sundaresan Iyer ,  Alok Baluni ,  Aaron Grenat

IPC: G06F1/04 ,  H03K3/012 ,  H03L7/08 ,  H03K19/20

CPC classification number: G06F1/04 ,  G06F1/10 ,  H03K5/00006 ,  H03K19/0013 ,  H03K19/20

Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

Abstract translation: 时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有 分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地 向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一与非门的输出而提供第一和第二控制信号 第一和第二NAND门。