公开(公告)号：US20150026406A1

公开(公告)日：2015-01-22

申请号：US13946120

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Edward J. McLellan ,  Sudha Thiruvengadam ,  Douglas R. Beard ,  Carl D. Dietz ,  Stephen V. Kosonocky

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache.

Abstract translation: 通过各种方式来调整处理系统的高速缓存的大小，使得每组高速缓存具有相同数量的方式。 高速缓存是集合关联缓存，其中每个集合包括多种方式。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。 例如，响应于处理器核心指示其进入减少活动的时段，高速缓存控制器可以减少高速缓存的每组中可用的路数。

公开(公告)号：US20150026407A1

公开(公告)日：2015-01-22

申请号：US13946125

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Edward J. McLellan ,  Sudha Thiruvengadam ,  Douglas R. Beard ,  Carl D. Dietz ,  Stephen V. Kosonocky

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3206 ,  G06F1/3275 ,  G06F12/0804 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14

Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.

Abstract translation: 当处理器进入选择的低功耗模式时，通过将存储在高速缓存中的数据写入存储器层次结构的其他级别来缓冲数据。 高速缓存的刷新允许减小高速缓存的大小，而不会在将减少的高速缓存位置处的数据写入存储器层次结构方面带来额外的性能损失。 因此，当高速缓存退出所选择的低功率模式时，通过将高速缓存的路数设置为最小数量，将其设置为最小大小。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。